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Fractional rate dataflow model for efficient code synthesis

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Authors
Oh, Hyunok; Ha, Soonhoi
Issue Date
2004-05
Publisher
Springer Verlag
Citation
Journal of VLSI Signal Processing, 2004, vol. 37, no. 1, pp. 41-51
Keywords
code synthesissynchronous dataflow (SDF)memory optimizationmultimedia
Abstract
Automatic code synthesis from dataflow program graphs is a promising high-level design methodology
for rapid prototyping of multimedia embedded systems. Memory efficient code synthesis from dataflow models has
been an active research subject to reduce the gap in terms of memory requirements between the synthesized code
and the hand-optimized code. However, existent dataflow models have inherent difficulty of efficiently handling
data structures. In this paper, we propose a new dataflow extension called fractional rate dataflow (FRDF) in which
fractional number of samples can be produced and consumed. In the proposed FRDF model, a constituent data type
is considered as a fraction of the composite data type. Existent integer rate dataflow models can be easily extended
to incorporate the fractional rates without loosing analytical properties. In this paper, the SDF model is extended
to include FRDF, which can reduce the buffer memory requirements significantly, up to 70%, for some multimedia
applications. Extended SDF model with fractional rate has been implemented in our system design environment
called PeaCE(Ptolemy extension as Codesign Environment).
ISSN
0922-5773 (print)
1573-109X (online)
Language
English
URI
http://hdl.handle.net/10371/7437
DOI
https://doi.org/10.1023/B:VLSI.0000017002.91721.0e
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Computer Science and Engineering (컴퓨터공학부)Journal Papers (저널논문_컴퓨터공학부)
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