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Efficient Exploration of Bus-Based System-on-Chip Architectures
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Sungchan | - |
dc.contributor.author | Ha, Soonhoi | - |
dc.date.accessioned | 2009-08-21T04:24:33Z | - |
dc.date.available | 2009-08-21T04:24:33Z | - |
dc.date.issued | 2006-07 | - |
dc.identifier.citation | IEEE Trans.Very Large Scale Integration systems, vol. 14, pp. 681-692, July 2006 | en |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://hdl.handle.net/10371/7439 | - |
dc.description.abstract | Separation between computation and communication
in system design allows system designers to explore the communication architecture independently after component selection and mapping decision is made. In this paper, we present an iterative two-step exploration methodology for bus-based on-chip communication architecture for multitask applications. We assume that the memory traces from the processing components are given. The proposed methodology uses a static performance estimation technique extended for multitask applications to reduce the design space quickly and drastically and applies a trace-driven simulation to the reduced set of design candidates for accurate performance estimation. For the case that local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. Experimental results show that the proposed methodology achieves significant performance gain by optimizing on-chip communication only, up to almost 100% compared with an initial single shared bus architecture, in both two real-life examples, a four-Channel digital video recorder and an equalizer for OFDM DVB-T receiver | en |
dc.description.sponsorship | This work
was supported by the National Research Laboratory Program under Grant M1-0104-00-0015 and the IT Leading Research and Development Support Project funded by Korean MIC. | en |
dc.language.iso | en | en |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en |
dc.subject | Communication architecture | en |
dc.subject | design space exploration | en |
dc.subject | memory allocation | en |
dc.subject | multitask | en |
dc.subject | performance estimation | en |
dc.title | Efficient Exploration of Bus-Based System-on-Chip Architectures | en |
dc.type | Article | en |
dc.contributor.AlternativeAuthor | 김성찬 | - |
dc.contributor.AlternativeAuthor | 하순회 | - |
dc.identifier.doi | 10.1109/TVLSI.2006.878260 | - |
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