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A Retargetable Parallel-Programming Framework for MPSoC
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kwon, Seongnam | - |
dc.contributor.author | Kim, Yongjoo | - |
dc.contributor.author | Jeun, Woo-Chul | - |
dc.contributor.author | Ha, Soonhoi | - |
dc.contributor.author | Paek, Yunheung | - |
dc.date.accessioned | 2009-08-23T23:55:03Z | - |
dc.date.available | 2009-08-23T23:55:03Z | - |
dc.date.issued | 2008-07 | - |
dc.identifier.citation | ACM Trans. Des. Autom. Electron. Syst. 13, 3, Article 39 | en |
dc.identifier.issn | 1084-4309 | - |
dc.identifier.uri | https://hdl.handle.net/10371/7511 | - |
dc.description.abstract | As more processing elements are integrated in a single chip, embedded software design becomes
more challenging: It becomes a parallel programming for nontrivial heterogeneous multiprocessors with diverse communication architectures, and design constraints such as hardware cost, power, and timeliness. In the current practice of parallel programming with MPI or OpenMP, the programmer should manually optimize the parallel code for each target architecture and for the design constraints. Thus, the design-space exploration of MPSoC (multiprocessor systems-on-chip) costs become prohibitively large as software development overhead increases drastically. To solve this problem, we develop a parallel-programming framework based on a novel programming model called common intermediate code (CIC). In a CIC, functional parallelism and data parallelism of application tasks are specified independently of the target architecture and design constraints. Then, the CIC translator translates the CIC into the final parallel code, considering the target architecture and design constraints to make the CIC retargetable. Experiments with preliminary examples, including the H.263 decoder, show that the proposed parallel-programming framework increases the design productivity of MPSoC software significantly. | en |
dc.description.sponsorship | This research was supported by the BK21 project, SystemIC 2010 project funded by the Korean
MOCIE, and Acceleration Research sponsored by the KOSEF research program (R17-2007-086- 01001-0). This work was also party sponsored by ETRI SoC Industry Promotion Center, Human Resource Development Project for IT-SoC Architect. The ICT and ISRC at Seoul National University and IDEC provided research facilities for this study. | en |
dc.language.iso | en | en |
dc.publisher | Association for Computing Machinery (ACM) | en |
dc.subject | Embedded software | en |
dc.subject | multiprocessor system on chip | en |
dc.subject | software generation | en |
dc.subject | design-space exploration | en |
dc.subject | parallel-programming | en |
dc.title | A Retargetable Parallel-Programming Framework for MPSoC | en |
dc.type | Article | en |
dc.contributor.AlternativeAuthor | 권성남 | - |
dc.contributor.AlternativeAuthor | 김용주 | - |
dc.contributor.AlternativeAuthor | 전우철 | - |
dc.contributor.AlternativeAuthor | 하순회 | - |
dc.contributor.AlternativeAuthor | 백윤흥 | - |
dc.identifier.doi | 10.1145/1367045.1367048 | - |
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