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Performance Analysis of LDPC Coded DMT Systems with Bit-loading Algorithms for Powerline Channel

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Authors
Kim, Seong-Cheol; Kim, Kyong-Hoe
Issue Date
2007-03-26
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
ISPLC '07. IEEE International Symposium on Power Line Communications and Its Applications, pp. 234-239, 2007
Keywords
Bit-loadingDMTLDPCPLC
Abstract
This paper deals with two different approaches to
overcome unfavorable channel characteristics and to obtain
higher performance of PLC systems: Low Density Parity Check
(LDPC) coding and bit-loading algorithms for Discrete Multitone
(DMT) modulation. We analyze the performance of LDPC coded
DMT systems with bit-loading algorithms in terms of bit-error
rate and data rate. Simulations are performed with statistically
modeled in-home PLC channel and noise. Several bit-loading
scenarios and LDPC coding schemes are also considered. The
performances of the proposed DMT systems with and without
LDPC codes are analyzed for the broadband PLC system design.
Language
English
URI
http://hdl.handle.net/10371/7804
DOI
https://doi.org/10.1109/ISPLC.2007.371129
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Others_전기·정보공학부
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