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Showing results 1 to 9 of 9

Issue Date	Title / Author(s) / Citation	File	Altmetrics
2009	Design of fully integrated CMOS 40-Gbs serial link transceiver 김정겸	link
2019-03	A 15-Gb/s Sub-Baud-Rate Digital CDR Kim, Dongwook; Choi, Woo Seok; Elkholy, Ahmed; Kenney, Jack; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.54 No.3, pp.685-695	DOI
2019-08	Design of Wide-Range Clock and Data Recovery with Multi-Phase Oversampling Frequency Detection 박관서	view file link
2019-08	A Study on Combined Equalization and Timing Recovery for High Speed Links 손세욱	view file link
2020-08	A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS Kim, Dongwook; Ahmed, Mostafa G.; Choi, Woo-Seok; Elkholy, Ahmed; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.55 No.8, pp.2196-2205	DOI
2021-02	Design of Maximum-Eye-Tracking CDR with Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation 주혜윤	view file link
2023	Design Techniques for Clock Generation and Recovery in Serial Interface 정우송	view file link
2023	Design of High-Speed Receiver with Stochastic CTLE Adaptation and Dead-Zone Free PAM-4 PD 심민교	view file link
2023-11	A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift Lee, Kwang-Hoon; Park, Jung-Hun; Lee, Yongjae; Song, Yeonggeun; Roh, Seungha; Shim, Minkyo; Song, Yoonho; Jung, Woosong; Hwang, Young-Ha; Oh, Jonghyun; Choi, Woo-Seok; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.70 No.11, pp.4003-4007	DOI

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