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Issue Date	Title / Author(s) / Citation	File
2018-06	A 64 Gb/s 1.5 pJ/bit PAM-4 Transmitter with 3-Tap FFE and G(m)-Regulated Active-Feedback Driver in 28 nm CMOS Ju, Haram; Choi, Moon-Chul; Jeong, Gyu-Seob; Jeong, Deog-Kyoon 2018 IEEE SYMPOSIUM ON VLSI CIRCUITS, pp.51-52	DOI
2021-11	A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS Lee, Kwangho; Jung, Woosong; Ju, Haram; Lee, Jinhyung; Jeong, Deog-Kyoon IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC 2021)	DOI
2021-11	Y A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS Ju, Haram; Lee, Kwangho; Jung, Woosong; Jeong, Deog-Kyoon IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC 2021)	DOI