Crack-free and high efficiency III-V multi-junction solar cell grown on vicinal Si(100) substrate

Abstract

The primary goal of this research is to fabricate crack-free and high efficiency III-V multi-junction solar cells on Si. In order to achieve the final goals, this research has been focused on three parts: growth of GaAs on Si using LP-MOCVD, investigation of impacts of crack formation on the solar cell device, and the fabrication of crack-free device. First, the device structures were grown on Si using LP-MOCVD using two-step growth modes, InGaAs/GaAs superlattice structure, and cycle annealing. By using two-step method, pure GaAs with flat surfaces were successfully grown on Si suppressing SK growth modes. In order to reduce the threading dislocation density (TDD) in GaAs layer, the in-situ cycle-annealing was performed in MOCVD chamber followed by In0.1Ga0.9As/GaAs structure. During the in-situ annealing, the AsH3 gases was introduced to prevent the evaporation of As from the GaAs layer. As the annealing-temperature increased from 700 to 820 oC, crystal quality was improved. The final GaAs buffer layer showed 6.0 x 10cm-7 value of TDD, and 146 arc sec FWHM of (004) rocking curves. On the top of buffer layer, the III-V GaAs solar cell epitaxial layers were grown. The device performance were measured under AM 1.5g condition, the conversion efficiency was 10.14, and 15.47 %, for the device on the buffer layer grown with only two-step growth modes, and for the device on the buffer layer grown on two-step growth modes, and InGaAs/GaAs structure, and cycle annealing, respectively. The improvement of efficiency was due to the enhancement of short-circuit current density and open-circuit voltage. Based on the analysis of time resolved photoluminescence and external quantum efficiency measurements, these enhancements were due to the increase of minority carrier lifetime from 0.096 to 0.9 ns. The total thickness of epitaxial layer was 5.8 m including 2.4 m GaAs buffer layer on Si substrate, which was above the critical thickness of crack formation. All of devices contained the crack arrays, where the crack linear density was varied from 4 to 126 cm-1. The impacts of crack formations on the device performance was investigated using TCAD simulations. Simulation results predicted that crack formations have the significant impacts on conversion efficiency especially due to reduction of open-circuit voltage in photovoltaic cells. At crack linear density with 200 cm-1, open-circuit voltage can be degraded to 86 % resulting in reduction of conversion efficiency from 24 % to 17% at 1105 cm-2 value of TDD. Based on the properties of recombination process at the GaAs surface, I assumed that the cleaved {110} surfaces have high surface recombination velocity as high as 3106 cm/s. This approach predicted reasonable the efficiency of GaAs photovoltaic cells on Si substrate. Finally, the control of crack propagation was investigated using stress concentrators in order to obtain crack-free III-V compound solar cells on Si. The notch type patterns introduced into the Si substrate were found to successfully generate the crack-free areas of a 2 mm × 2 mm size separated by the cracks for the 5.8 m-thick III-V compound semiconductor layers on it. The population of crack arrays was investigated in the wafer scale. The crack linear density was significantly reduced from 22.25 cm-1 to 1.10 cm-1 by controlling crack arrays. The value of 1.10 cm-1 crack density was due to unintentional crack arrays, which were generated with surface defects or particles underlying before growth. By measuring dark I-V curves between adjacent cells, the individual solar cells on the crack-free areas were confirmed to be electrically isolated one another with the well-defined crack array, replacing conventional Mesa isolation process, which has undercut issue and area loss. The best cell efficiency was increased from 16.44 % for the device containing 16.8 cm-1 crack linear density, to 18.17 % for the device with crack-free conditions under AM 1.5g condition. The maximum efficiency under concentration was 19.8, 18.5, and 23.5 % for crack-free device, the device containing 16.8 cm-1 crack linear density, and the reference GaAs/GaAs cell, respectively. Above 10 suns of concentration level, cell efficiency reduced with the reduction of fill factor. The J-V curves showed that the reduction of fill factor was due to the parasitic resistance in the device. Based on analysis of dark J-V curves, the parasitic resistance was 0.43. . In order to increase maximum efficiency, the parasitic resistance should be reduced with the optimized metal grid design and the metal deposition process for the centration operation