Design and Fabrication of Gate Driver Circuits Employing Depletion-Mode Oxide TFTs for AMLCD and AMOLED

Abstract

Recently, the high-end flat panel display (FPD) requires ultrahigh-resolution (≥4Kx2K) and high-frame-rate (≥240Hz). However, it is well known that the electrical characteristics of the widely used a-Si:H TFT could not meet the requirements. The amorphous oxide-based thin-film transistors (TFTs) have attracted considerable attention due to high mobility and good uniformity over large area substrates. Most oxide-based TFTs are inherently a depletion-mode device rather than the widely used enhancement-mode device due to large electron concentrations. In addition, it is well known that a severe negative shift in the threshold voltage of oxide-based TFTs occurs during negative bias illumination stress or only light illumination. Therefore, the driving circuit which can be operated in depletion-mode would be indispensable for an oxide TFT-based display. In this study, novel level shifters and shift registers employing depletion-mode a-IGZO TFTs were investigated. The level shifter employing two clock signals with 180◦ out of phase and one discharging TFT has been swung fully from VDD to VSS. Although the level shifter employed only n-type depletion-mode a-IGZO TFTs, it had a wide swing output without any additional power sources and input signals. The shift register (I) has been designed by employing two low-voltage-level power signals with which a negative voltage can be applied to the Vgs of depletion-mode a-IGZO TFTs. Especially, the shift register (II) has been designed by employing only one low-voltage-level power signal, which has been usually used in a circuit employing a conventional enhancement-mode device, without an additional signal. The shift registers successfully exhibited a high-voltage output pulse without any distortion. For the narrow-bezel display, the shift register (III) employing node-shared structure, where Q-node and Qb-node of adjacent two stages are shared, respectively, required 14 TFTs, 3 clock lines, and 3 power source lines for two output pulses, whereas the previous shift registers consisted of more than 22 TFTs, 4 clock lines, and 6 power source lines. For the applications of the driving circuits in displays, such as AMLCD and AMOLED, the depletion-mode a-IGZO TFT shift registers embedded with a full-swing level shifter were investigated. The start signal and the clock input signals of −10∼5 V have been level shifted to the output signals of −10∼20 V. The depletion-mode a-IGZO TFT shift register embedded with a full-swing level shifter has successfully exhibited a high-voltage output pulse without any distortion. Also, the shift register embedded with the level shifter successfully exhibited a high-voltage output pulse without distortion at a clock frequency of 100 kHz, which is enough to drive a high-frequency FPD with a frame rate of ∼360 Hz and a resolution of FHD. The SPICE simulation results have shown that the shift register embedded with the level shifter would work without any problem, although the threshold voltages of the TFTs degraded by gate bias stress in the level shifter and the shift register would be largely shifted to −9.3 and +15.2 V, respectively. The measured output waveform of the shift register embedded with the level shifter has not been distorted after 240-h driving under 450-nm illumination with an intensity of 1 mW/cm2 at 60 ◦C.