Gated Twin-Bit (GTB) SONOS NAND Flash Memory for High Density Nonvolatile Memory

Abstract

In this dissertation, the gated twin-bit (GTB) SONOS NAND flash memory is studied. To meet the demand of high density nonvolatile memory, a GTB SONOS array having a cut-off gate and two storage nodes at a single wordline is designed. By using the forward-reverse read scheme, the memory density can be increased to 2 bit per 4F2 area which is twice the conventional NAND array. Recent trend of nonvolatile memories are introduced, and the solutions of scaling down of NAND flash memory at this time is mentioned in Chapter 1 and 2. In Chapter 3, the GTB NAND device is introduced and the operation scheme of GTB NAND array is investigated with the TCAD simulation. In the case of program operation, the cut-off gate plays a role of preventing the channel potential transfer and enables separate programming. In the case of read operation, forward-reverse read scheme is used to read the bits with a common wordline. Fabrication processes are introduced, and several important issues in the GTB array are verified. The process flow and images of fabricated GTB SONOS devices are presented, and electrical characteristics are measured in Chapter 4. In addition, a gated multi-bit (GMB) NAND array which can compete with recent 3-dimensional NAND structures is introduced in Chapter 5. This structure has single crystalline silicon channel and 2N bit per 4F2 memory density. Fabrication processes are stated, and operations are verified with simulation.