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WSe2 Field Effect Transistor Fabrication and Characterization

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Authors
조인탁
Advisor
이종호
Major
공과대학 전기·컴퓨터공학부
Issue Date
2016-02
Publisher
서울대학교 대학원
Keywords
TMDCWSe2field effect transistorpulsed-IVlow frequency noise
Description
학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 이종호.
Abstract
Recently, transition metal dichalcogenides (TMDCs) have been investigated as candidate materials for next generation nano electronic devices with their outstanding electrical, optical and thermo-mechanical properties. Among various TMDCs FET, especially WSe2 FET, has drawn attention to the possibility for its applications of nanoscale complementary circuits and switching back planes for high resolution flat panel display (FPD) due to their high mobility (~100 cm2/V·s), excellent on/off ratio (~107), and low subthreshold slope (SS, ~ 70 mV/decade).
In this thesis, high performance TMDC field effect transistors (FETs) were fabricated by mechanically exfoliated multi-layer WSe2. In the DC measurement result, large hysteresis is observed due to the gate bias stress during the measurement. However, in the Pulsed I-V measurement, negligible hysteresis gap and enhanced conductance are obtained with an optimized measurement condition (Vbase = 0 V, ton = 10-4 s and toff = 1 s). Adopting the hydrogen annealing and hydrophobic CYTOP encapsulation layer, the device performance has improved dramatically.
From the low frequency noise measurement result, fabricated multilayer WSe2 FET obey consistently Hooges empirical relation, which indicates mobility fluctuation is a dominant mechanism responsible for the drain current fluctuation. Although low frequency noise measure at different temperature, the mechanism of low frequency noise is not changed. However, Hooge`s parameter slightly increased with temperature increase due to phonon scattering enhancement. These results are explained with the help of model incorporating Thomas-Fermi charge screening and inter-layer resistance coupling.
High performance complementary metal oxide semiconductor (CMOS) logic inverter was implemented by fabricating p-and n-type field effect transistors (FETs). Both the p-type FET with a high work-function metal and the n-type FET with a low work-function metal show similar on-current densities (>106A) and on/off current ratios (>104). The proposed inverter shows excellent switching characteristics including relatively high voltage gains and high noise margins. This work has great significance in terms of realization of CMOS logic device based on TMDCs without additional doping scheme.
Lastly, contact property improve using an oxygen plasma treatment method. After plasma treatment, WO3 ¬was formed at WSe2 flake surface. WO3 plays a role as hole injection layer between Ni and WSe2 flake. Contact resistance and undesirable Schottky barrier height reduced dramatically. This has the advantage of being easy to process and method do not need an additional deposition process.
Language
English
URI
https://hdl.handle.net/10371/119187
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Ph.D. / Sc.D._전기·정보공학부)
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