Performance Enhancing Technique for the Successive Approximation Analog-to-digital Converter

Abstract

This thesis is written about a performance enhancement technique for the successive-approximation-register analog-to-digital converter (SAR ADC). More specifically, it focuses on improving the resolution of the SAR ADC. The basic operation principles and the architecture of the conventional SAR ADC is examined. To gain insight on areas of improvement, a deeper look is taken at the building components of the SAR ADC. Design considerations of these components are discussed, along with the performance limiting factors in the resolution and bandwidth domains. Prior works which challenge these problems in order to improve the performance of the SAR ADC are presented. To design SAR ADCs, a high-level modeling is presented. This model includes various non-ideal effects that occur in the design and operation. Simulation examples are shown how the model is efficient and useful in the initial top-level designing of the SAR ADC. Then, the thesis proposes a technique that can enhance the resolution. The SAR ADC using integer-based capacitor digital-to-analog converter (CDAC) exploiting redundancy is presented. This technique improves the mismatch problem that arises with the widely used split-capacitor structure in the CDAC of the SAR ADC. Unlike prior works, there is no additional overhead of additional calibration circuits or reference voltages. A prototype SAR ADC which uses the integer-based CDAC exploiting redundancy is designed for automotive applications. Measurement results show a resolution level of 12 bits even without any form of calibration. Finally, the conclusion about the operation and effectiveness on the proposed technique is drawn.