Design of Injection-Locked PLL with Digital Calibration of Frequency Error and Path Mismatch

Abstract

A novel injection technique for the extension of the noise-filtering band-width is proposed to filter out an oscillators noise in high frequency region. In addition, injection-locked phase-locked loops (IL-PLL) are proposed to mini-mize a frequency error fERR and a path mismatch pERR. Here, fERR is defined as the frequency difference between the free-running frequency of an oscillator and the desired frequency. Besides, pERR includes a non-ideal delay and a de-vice mismatch. This thesis insists two IL-PLLs using different calibration loops. First, an IL-PLL using a charge-stored complementary switch (CSCS) injec-tion technique is proposed. The IL-PLL exhibits a wider locking range com-pared to other conventional IL-PLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency error calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jit-ter and reference spur. The prototype chip fabricated in 65-nm CMOS technol-ogy achieves a 285-fsrms integrated jitter at 3.328 GHz from the reference clock of 52 MHz while consuming 7.16 mW. The figure-of-merit of the IL-PLL is −242.4 dB. Second, an IL-PLL offering an excellent spur level with a time-division dual calibration (TDDC) scheme is proposed. The TDDC employs a replica delay cell in the injection-locked oscillator to detect and eliminate both a frequency error and a path mismatch. Robustness of the TDDC is verified over multiple samples by varying the supply voltage. With the TDDC enabled, the prototype chip fabricated in 65-nm CMOS technology achieves the spur reduction of 23 dBc, resulting in the spur level of -65 dBc. The integrated jitter at 2.5 GHz from the reference clock of 156.25 MHz is 198 fsrms while consuming 13.5 mW from a 1.1 V supply. The figure-of-merit of the IL-PLL is ‒242.8 dB.