Characteristics of La-incorporated TiN and Ru-based metal gates on Hf-based Gate Dielectrics for CMOSFETs

Abstract

The minimum feature size, including gate oxide thickness, of complementary metal oxide semiconductor field effect transistors (CMOSFETs) has decreased exponentially until now. However, with this method, scaling slows down at the 90 nm node as SiO2 runs out of atoms and further scaling is limited due to the increase of gate-leakage current. To continue the scaling of transistors, various high-k oxide materials have been studied intensively for the past few decades. The semiconductor industry has already converged on Hf-based oxides for the first generation CMOS products featuring high-k gate dielectrics and metal gate electrodes. However, even though various metal materials were already used on Hf-based oxides, there are still several crucial problems that need to be considered

an effective work function (EWF) modulation for adjusting the threshold voltage (Vt) of transistors and further scaling of equivalent oxide thickness (EOT), which was approximately 1.0 nm for the first generation high-k/metal gate device. Continued gate length (Lg) scaling for the 32 nm and beyond with a planer structure requires sub-nm EOT to suppress short-channel effects. Fully depleted device structures, such as FinFET or extremely thin SOI (ETSOI), improve short-channel control and thus relax the requirements for EOT scaling. However, the insertion point of such device architectures is expected to be the 22 nm and beyond and sub-nm EOT may be still required at those advanced technology nodes. To meet continued EOT scaling until the turning point in device architectures, mainly three possible EOT scaling approaches are studied in this work: (1) a high-k material with k-value greater than that of HfO2 (so-called higher-k), (2) the physical thickness reduction of interfacial layer (IL) (so-called scavenging), (3) suppression of low-k dielectric layer between metals and dielectrics (so-called deadlayer effect). Firstly, the relation between the permittivity and microstructures of atomic layer deposited Hf1-xSixOy (HfSiO) thin films with different Si concentrations as a function of post-deposition annealing (PDA) temperature was investigated. The PDA at high temperature results in the separation of crystallized HfO2 phase from the much higher Si-containing amorphous-like matrix. Tetragonal phase HfO2 formation with higher permittivity than the monoclinic HfO2 phase is induced with an appropriate Si concentration in the film (~10–20%). In the crystallized HfSiO film, the Si concentration in the phase-separated HfO2 (mainly consisting of HfO2) could be controlled by PDA temperature, which determines the degree of phase separation. The increased PDA temperature reduces the Si concentration in the phase-separated HfO2 which induced monoclinic phase formation. Therefore, the PDA temperature for maximized permittivity of the crystallized HfSiO films (maximized tetragonal phase portion in the film) depends on the Si concentration of the HfSiO film in the as-deposited state. However, considering the maturity of Hf-based high-κ gate dielectrics, scaling SiO2-based IL in conjunction with Hf-based oxides may be more practical in meeting the requirements for the 22 nm technology node and beyond. Secondly, lanthanum (La)-incorporated TiN metal gates, such as TiN/La/TiN (TLT) and TiLaN (TLN), on HfO2/Si substrates were investigated focusing on the flat band voltage (VFB) modulation for nMOS and IL scaling to almost zero. The maximum VFB modulation value of the TLT/HfO2/Si stack was −423 mV compared to the VFB of the TiN single metal case, which is superior to that of TLN (−247 mV). This is because the TiN barrier layer in the TLT metal stack prevents interfacial oxidation. Both TLT and TLN gate metals effectively shrink the IL thickness to values below 0.5 nm. In the case where the TLT metal gate was annealed at 600 oC for 30s, the IL thickness was almost zero and the equivalent oxide thickness (EOT) was decreased to 0.8 nm even though the maximum temperature was limited to 600oC. However, the La-incorporated TiN metal gates can not adopt for pMOS due to their low work function, and another method must be pursued to scale the EOT of p-type MOSFET. Thirdly, the influences of RuO2 metal gate on the dielectric performance of high-k HfO2 film on Si substrate were examined. Dielectric materials with a higher-k value also suffer from a dead-layer effect that the effective dielectric constant decreases with decreasing thickness, which becomes even more serious as the bulk k value increases. The EOT of HfO2 film can be scaled down by ~ 0.5 nm in the EOT range from 0.8 to 2.5 nm compared with the standard Pt gate case by using the electrically conducting RuO2 without sacrificing any other performance of the MOS capacitor. RuO2 is one of the rare materials, which contain polarizable ions, high electrical conductivity, and high work function (WF) which is necessary for the p-type MOSFET. This was attributed to the suppression of the dielectric dead-layer effect at the HfO2/RuO2 interface due to the possible ionic polarization of RuO2 within the screening length of the electrode. In addition, the estimated work function of RuO2 on HfO2 is ~ 5.0 eV suggesting the appropriateness of RuO2 for p-MOSFET. Finally, RuO2 metal gates were fabricated by a reactive sputtering method under the different O2 gas ratio. For the given sputtering power of 60 W, ~ 13 % O2 ratio was the critical level below or over which RuO2 film have hyperstoichiometric and stoichiometric compositions, which resulted in the effective work function difference by ~ 0.2 eV. The stoichiometric RuO2 film imposed almost no damaging effect to the underlying SiO2 and HfO2 gate dielectrics. RuO2 gate decreased the equivalent oxide thickness by ~ 0.5 nm and leakage current by ~ two orders of magnitude compared with the Pt-gated samples.