Design of an Efficient Capacitor-Free Piezoelectric Energy Harvesting PMIC

Abstract

This research suggests a design methodology of an efficient piezoelectric power management IC which removes the large intermediary buffer capacitor and achieves a high end-to-end energy efficiency that can theoretically be 100%. A prototype IC designed and simulated on a 0.18-μm HVCMOS process showed 460% enhancement on the case of continuous input vibration with respect to the full-bridge diode topology, and showed 61% end-to-end efficiency for a batteryless wireless switch application which is 1.7 times higher than the ideal efficiency of a capacitor-based topology.