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Investigation of Cell Disturbance and Fast Transient Effect in Charge Trap NAND Flash Memories : 전하 트랩 방식의 낸드 플래시에서의 셀 디스터번스

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Authors
최병인
Advisor
이종호
Major
공과대학 전기·컴퓨터공학부
Issue Date
2014-02
Publisher
서울대학교 대학원
Keywords
Charge Trap (CT) NAND flash memoryDisturbance3-D Stack NAND
Description
학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 이종호.
Abstract
Trap-based NAND flash memory has several advantages which may help in overcoming conventional FG NAND flash memories limitation due to simple lower gate stack and less electrical coupling with dielectric storage layer. Understanding the cell characteristics of charge trap type (CT) NAND flash memory is essential including the state-of-the-art three-dimensional (3-D) stack NAND flash memories.
In this thesis, first of all, the cell-to-cell interference in CT NAND flash memory is systematically analyzed by separating the total Vth shift in inhibit cells into each component. From this analysis, bit-line (BL) cell-to-cell interference is larger than word-line (WL) one, which means that the channel coupling by adjacent program string to inhibit string gives larger effect than capacitive coupling to adjacent nitride storage nodes along the string for CT NAND flash memories. For inhibit cells in unselected strings, we proposed a new programming bias method for 2-D NAND and 3-D stacked NAND flash memories. Key point of our method is to store electrons in the edge WL cell by applying a Vpass before channel cut-off and then distribute the electrons along the channel before program execution. As a result, we can reduce the high boosted channel potential during programming, which effectively suppresses hot-carrier generation between the boosted channel and the string select line (SSL) device. Also, the program disturbance characteristics in the three-dimensional (3-D) stack NAND flash was analyzed for the first time in terms of SSL Vth and p-type body doping profile. From detail simulation works, we suggested the optimized process window of SSL device in the view point of efficient boosting performance of the 3-D stack NAND flash memory.
Second, the read-disturbance observed newly in unselected WL cells of unselected strings in 3-D stack NAND flash memory has been analyzed in detail by characterizing the results from measured 2-D TANOS NAND flash and device simulation. The read disturbance in unselected strings is attributed to the boosted channel potential incurred by turning off the select devices of unselected cell strings when selected and unselected WL cells have different state (P or E). Measured and simulated results verified that proposed method by us can suppress the read disturbance effectively. During read operation, we observed the current transient by pre-pulse in the CT NAND with high-k dielectric as blocking oxide. As increasing the pre-pulse width and bias, current transient is getting larger to be the same current level of conventional dc measurement. Fundamental cause of the transient behavior is attributed to electron trapping and de-trapping from the control-gate to the high-k dielectric (Al2O3). For a single device, the time for stabilization in erased state is longer than that in programmed state. However, in a device in a string, the tendency is opposite due to geometric effect.
Consequently, in this thesis, the cell disturbance characteristics and trap behavior of CT NAND Flash memories has studied in detail by measurement and simulation works. This work is very meaningful to implement CT NAND Flash memories for the next generation nonvolatile memory.
Language
English
URI
https://hdl.handle.net/10371/123025
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Master's Degree_전기·정보공학부)
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