Analysis of leakage current according to the impact of bulk traps in strained n-FinFETs

Abstract

A strained n-type FinFET which uses SiGe buffer layer for tensile stress is designed based on CMOS technology. This device generates bulk traps because of the lattice mismatch between SiGe layer and silicon layer. This structure is simulated in order to investigate the impact of bulk trap on the leakage current. It is observed that the leakage current is generated mainly in the region of top of the Fin because electric field is concentrated. For specification, Fin is divided in to four portions according to the Fin height. It is observed that the leakage current is generated 42%, 29%, 26%, and 3% from top to bottom. The impact of bulk-traps is analyzed by simulation. It is assumed that the bulk-traps are acceptor like trap which is distributed uniformly. The bulk traps are located in the spacer region which is important in analyzing leakage current. The numbers of bulk traps in each region are assumed to be identical for comparison. The simulation results show that the leakage current decreases when the bulk traps exist. The decrease rate decreases from top to bottom and there is marginal difference in the bottom region of the Fin. When the traps capture the electrons, an energy barrier is formed resulting in increase of the tunneling distance. Also, the peak electrical field decrease because of the traps.