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A Silicon Surface Ion-Trap Chip with Dielectric Sidewalls Shielded by Metal Films : 절연층 측벽을 금속 박막으로 보호한 실리콘 평면 이온트랩 칩

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dc.contributor.advisor조동일-
dc.contributor.author홍석준-
dc.date.accessioned2017-10-27T16:40:54Z-
dc.date.available2017-10-27T16:40:54Z-
dc.date.issued2017-08-
dc.identifier.other000000146069-
dc.identifier.urihttps://hdl.handle.net/10371/136791-
dc.description학위논문 (박사)-- 서울대학교 대학원 공과대학 전기·컴퓨터공학부, 2017. 8. 조동일.-
dc.description.abstractAn ion trap is a device to confine charged particles by utilizing electromagnetic fields. Since the trapped ions have a feasibility of the individual state manipulation, a long coherence time, and an ideal isolation from the surroundings, the ion-trap technology becomes one of the leading candidates for the physical implementation of quantum information processing. In order to build a large-scale integrated ion-trap system for realizing complex quantum algorithms, microfabrication technologies have been applied to construct ion traps. The use of micro-electro-mechanical system (MEMS) ion-trap chip allows a scalable architecture of ion-trap arrays and integration of functional components to the trap chip, but a few side effects also arise. One of the most particular problems is stray fields generated by the charges accumulated on the sidewalls of thick dielectric pillars or the native oxide grown on metal surfaces, since the stray fields lead to ion micromotions which can cause heating and escape of the trapped ions. This dissertation presents a silicon surface ion-trap chip with dielectric sidewalls shielded by metal films. The oxide pillars supporting the top electrodes are fabricated to have overhang structures, and the upper and lower part of the pillars are coated by separate aluminum layers which are electrically isolated from each other. In order to evaluate the effects of the native metal oxide on the electrode surface to the charging phenomenon, a trap chip with an additional gold layer on the aluminum electrodes is also fabricated. An ultra-high vacuum (UHV) chamber, electrical connections, and an optical setup are prepared to trap 174Yb+ ions, and the ions are successfully trapped by using the experimental setup including the fabricated ion-trap chip. To evaluate the effectiveness of the proposed electrode structures, charging is intentionally induced on the chip surface by injecting a 355-nm pulse laser with 40-μW power perpendicularly to the chip surface. The intensity of the stray field is estimated by measuring the displacement of ion position after charging is induced. When the Al-based chips with exposed and Al-coated dielectric sidewalls are used, the standard deviation of the intensities of stray fields are 3.53, and 5.63 V/m, respectively. However, the standard deviation of the intensity of stray fields in the case of using Au-coated chip is 1.56 V/m, and any stray field is measured when the laser was injected on the surface or sidewalls of the gold-coated electrodes. These experimental results indicate that the gold coating on the surface of the aluminum electrodes and the sidewalls of dielectric pillars is effective for eliminating the generation of stray fields induced by static charges.-
dc.description.tableofcontentsChapter 1. Introduction 1
1.1 Quantum Information Processing and Qubit 1
1.2 Ion Trap as a Qubit Platform 3
1.3 Development of Surface Ion Trap 5
1.4 State-of-the-Art of Surface Ion Trap 8
1.4.1 Advanced Technologies 8
1.4.2 Current Challenges 13
1.5 Document Overview 17
Chapter 2. Design 20
2.1 Structural Design 20
2.1.1 General Considerations for Structural Design 20
2.1.2 Proposed Structure 24
2.2 Layout Design 27
2.2.1 Considered Parameters 27
2.2.2 Simulation of Electric Potential 33
2.2.3 Electrode Dimensions and Chip Shape 39
Chapter 3. Fabrication 50
3.1 Material and Equipment 50
3.2 Aluminum Trap 54
3.2.1 Fabrication Process 54
3.2.2 Fabrication Result 63
3.3 Gold Coating on the Aluimnum Trap 71
3.3.1 Fabrication Process 71
3.3.2 Fabrication Result 75
3.4 Chip Packaging 79
Chapter 4. Experiments 83
4.1 Trapping Ions 83
4.1.1 Vacuum Chamber and In-Vacuum Components 83
4.1.2 Electrical and Optical Setup 88
4.1.3 Trapping ions 94
4.2 Dielectric Charging 96
4.2.1 Experimental Setup 96
4.2.2 Experimental Result 104
Chapter 5. Conclusion and Future Works 109
5.1 Conclusion 109
5.2 Future Works 112
Bibliography 114
Abstract in Korean 126
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dc.formatapplication/pdf-
dc.format.extent19369584 bytes-
dc.format.mediumapplication/pdf-
dc.language.isoko-
dc.publisher서울대학교 대학원-
dc.subjectIon trap-
dc.subjectMicrofabrication-
dc.subjectQuantum information processing-
dc.subjectDielectric charging-
dc.subjectStray field-
dc.subject.ddc621.3-
dc.titleA Silicon Surface Ion-Trap Chip with Dielectric Sidewalls Shielded by Metal Films-
dc.title.alternative절연층 측벽을 금속 박막으로 보호한 실리콘 평면 이온트랩 칩-
dc.typeThesis-
dc.description.degreeDoctor-
dc.contributor.affiliation공과대학 전기·컴퓨터공학부-
dc.date.awarded2017-08-
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