An Access-Pattern-Aware Page Placement Algorithm for the Hybrid Memory Architecture

Abstract

Due to the high memory footprint pressure, the hybrid memory architecture consisting of small-sized DRAM and large-sized PCM has been regarded as a promising approach. This architecture aims at (1) alleviating the high power consumption caused by large-sized DRAM, and (2) harnessing the non-volatility and in-place update capability of PCM. Numerous studies have addressed the importance of page placement scheme between two different types of memory frames. Particularly, they have made every effort to provide good wear-leveling, hide the low write speed of PCM and reduce the power consumption. However, they lack one of the two points: (1) read-dominated workloads also decrease the system-wide energy efficiency and (2) excessive page migration should be avoided. In order to solve the abovementioned problems, we propose an access-pattern- aware page placement algorithm. Fundamentally, it uses page-leveling policy using multi-queue. To set the level of a page, it uses weighted access counting which puts a more emphasis on write accesses without ignoring read accesses. To minimize the number of migrations from DRAM to PCM, it performs state-transition-based recency checking for pages in DRAM. Our experimental results clearly demonstrate that it can reduce the average memory access time by up to 39% and the power consumption by up to 57%, respectively, compared to the previous approaches. Furthermore, they show that the PCM wear-out performance can be improved by 27%.