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Evaluation of deposited silicon oxide with post-deposition annealing for gate oxide of MOS capacitors on 4H-SiC

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dc.contributor.advisor김형준-
dc.contributor.author이수형-
dc.date.accessioned2018-05-28T16:14:33Z-
dc.date.available2018-05-28T16:14:33Z-
dc.date.issued2018-02-
dc.identifier.other000000150065-
dc.identifier.urihttps://hdl.handle.net/10371/140618-
dc.description학위논문 (박사)-- 서울대학교 대학원 : 공과대학 재료공학부, 2018. 2. 김형준.-
dc.description.abstractSilicon carbide (SiC) is one of the promising materials being developed for the application of power devices. The 4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) using 4H-SiC as substrate are expected to play a major role as a power semiconductor device. However, carbon clusters, which are formed in the oxidation process, increase interface states, and thus deteriorate device performance. Many researches have reported that the efficient method to remove the interfacial traps is the post-oxidation annealing (POA) using nitric oxide (NO) gas, which has become common process to remove interface traps. Although NO POA is effective on reducing interface traps, it is necessary to find the alternative and advanced methods to reduce interface traps effectively: deposition is one of them, because the most of carbon clusters are formed during oxidation process. The deposition of oxide films has been usually carried out by chemical vapor deposition (CVD) and atomic layer deposition (ALD). ALD oxide with NO post-deposition annealing (PDA) showed excellent performance was reported, but the MOSFET, which was fabricated with the ALD oxide, consisted of thin oxide less than 30 nm. However, the commercial products commonly used thicker than 50 nm. In this dissertation, oxide films thicker than 40 nm were deposited by ALD or sputtering, and then MOS capacitors were fabricated to evaluate their electrical and physical properties. And the effects of PDA conditions on the deposited oxide were also investigated. In addition, to evaluate the feasibility of oxide deposition without PDA, the oxides, which were deposited on the thermal buffer oxide, were also investigated.
In order to densify the 50 nm SiO2 oxide film deposited with plasma-enhanced ALD (PEALD), the PDA was performed using Ar gas, which is an inert gas. At this time, the PDA was operated at 400, 600, 800, 1000, and 1200°C for 2 h. HF etch test and leakage current analysis showed that the oxide film was stabilized after densifying at 1000°C or higher. However, in the capacitance‒voltage (C‒V) characteristics, the densified sample at 1000°C was found to be in a less stable state, but a stable oxide film was formed only at 1200°C. In addition, the NO PDA, known to be effective at 30 nm, was conducted for 2 h at 1200°C on PEALD oxide. The C‒V hysteresis decreased significantly compared to the as-dep oxide, but the flat-band voltage (VFB) shifted significantly in the negative direction. This is because the thicker the oxide film, the greater the positive charging by nitrogen atoms.
On the other hand, sputtering is a traditional physical vapor deposition (PVD) method, but it has not been often used to deposit the gate insulating films. To evaluate whether this sputtering SiO2 oxide film can be used as an insulating film, MOS capacitors with sputtered oxide were fabricated and their electrical properties and physical properties were also analyzed. N2, NH3, O2, and NO PDA were conducted to stabilize the sputtered oxide. All the samples were found to be sufficiently densified through refractive index measurement and HF etching test, and in the case of O¬2 PDA, an additional oxidation reaction occurred. As a result of the insulation property evaluation, N2 and NH3 did not have good insulation characteristics, which seems to be the result of the chemical reaction of nitrogen, increasing the leakage current. In the case of O2 and NO, they showed insulation characteristics but it was insufficient compared to thermal oxide. For the optimization of NO PDA for sputtering oxide, the 30, 60, and 90 min of NO PDAs were also investigated. As PDA time increased, VFB was negatively shifted and hysteresis decreased. As a result of normalized conductance‒frequency (GP‒ω) and Dit characteristics, the lowest interface traps were shown in the 60 min NO PDA among three conditions.
Since both PEALD and sputtering use plasma, it is necessary to judge whether the plasma damage affects the substrate and interface characteristics. A passivation layer was formed through pre-oxidation before deposition, and then an oxide film was formed through PEALD and sputtering. As-deposition oxide without PDA showed poor insulating properties and large leakage current. However, pre-oxidation greatly reduced the leakage current and allowed a normal C‒V curve to be obtained. Although the leakage current is not as good as that of the thermal oxide, the overall characteristics are sufficiently improved for both PEALD and sputtering oxide. Based on these results, pre-oxidations using NO and N2O were conducted, and showed superior C‒V characteristics when using N2O and NO/O2 mixed gas.
In this dissertation, whether the deposition SiO2 can be used as the gate oxide was investigated. To improve characteristics of PEALD and sputtering SiO2, post-deposition annealing and pre-oxidation were conducted. The applicability of PEALD and sputtering oxide was investigated through PDA and pre-oxidation under various conditions. If the deposition and annealing conditions were optimized, deposition oxide will have competitive enough to be used as a gate oxide for 4H-SiC MOS device.
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dc.description.tableofcontentsChapter 1. Introduction 1
1.1 SiC Power Device 1
1.1.1 Power device 1
1.1.2 Conventional MOS Device 5
1.1.3 Application of SiC for power device and SiC MOS device 7
1.2. Material Properties of SiC 9
1.2.1 Structural properties 9
1.2.2 Thermal properties 12
1.2.3 Optical properties 14
1.2.4 Electrical properties 16
1.3 Gate Oxide Issue for SiC MOS Device 20
1.3.1 Conventional SiC MOSFET 20
1.3.2 The formation of defect between SiO2/SiC interface 23
Chapter 2. Literature Review 27
2.1 Fabrication Method of Gate Oxide 27
2.1.1 Thermal oxide on SiC 27
2.1.2 CVD oxide 31
2.1.3 ALD oxide 33
2.1.4 PVD oxide 35
2.2 Nitridation of SiO2 on SiC for MOS device 37
2.2.1 NO and N2O post-oxidation annealing 39
2.2.2 N2 post-oxidation annealing 43
2.2.3 Other nitridation methods 45
2.3 Basic of Device Measurement 49
2.3.1 C‒V measurement 49
2.3.2 Interface state density measurement 54
2.3.3 J‒E measurement 58
2.4 Electrical Characteristics of Gate Oxide on SiC 60
2.4.1 Thermal oxide 60
2.4.2 CVD oxide 63
2.4.3 ALD oxide 67
2.4.4 PVD oxide 73
Chapter 3. Experiment and Analysis 78
3.1 Sample Preparations 78
3.1.1 4H-SiC wafer information 78
3.1.2 Wafer cleaning process 78
3.2 Gate Oxide Deposition and Oxidation 79
3.2.1 Plasma-enhanced atomic layer deposition system 79
3.2.2 PEALD conditions of gate oxide deposition 80
3.2.3 Sputtering system and deposition condition 82
3.2.4 Dry oxidation process 83
3.3 Post-deposition annealing process 85
3.3.1 Apparatus of furnace for PDA 85
3.3.2 Ar post-deposition annealing 85
3.3.3 NO post-deposition annealing 86
3.3.4 N2, NH3, O2 Post-deposition annealing 86
3.4 MOS Capacitor Fabrication 88
3.5 Measurement and Analysis 89
3.5.1 Physical and chemical analysis of gate oxide 89
3.5.2 Electrical properties measurement of MOS capacitor 90
Chapter 4. Results and Discussions 92
4.1 Characteristics of PEALD Oxide with PDA 92
4.1.1 Effects of Ar PDA 92
4.1.2 Effects of NO PDA on 50nm SiO2 99
4.2 Characterisitcs of Sputtered Oxide with PDA 102
4.2.1 Physical and chemical properties 102
4.2.2 J‒E and oxide breakdown characteristics 108
4.2.3 C‒V and Dit characteristics 111
4.3 Analysis of Sputtered Oxide with NO PDA 117
4.3.1 C–V curve analysis 117
4.3.2 Modeling of charging in near interface traps 121
4.3.3 G–ω and Dit analysis 124
4.4 Deposited Oxide with Thermal Oxide Interlayer 127
4.4.1 PEALD oxide with dry thermal oxide 127
4.4.2 PEALD oxide with NO thermal oxide 132
4.4.3 PEALD oxide with NO/O2 and N2O thermal oxide 135
4.4.4 Sputtering Oxide with dry thermal oxide 140
4.5 Experiments Summary 144
Chapter 5. Conclusions 146
CURRICULUM VITAE 148
REFERENCES 154
LIST OF PUBLICATIONS 163
국문 초록 171
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dc.formatapplication/pdf-
dc.format.extent7942829 bytes-
dc.format.mediumapplication/pdf-
dc.language.isoen-
dc.publisher서울대학교 대학원-
dc.subject4H-SiC-
dc.subjectMOS capacitor-
dc.subjectPEALD-
dc.subjectsputtering-
dc.subjectpost-deposition annealing-
dc.subject.ddc620.1-
dc.titleEvaluation of deposited silicon oxide with post-deposition annealing for gate oxide of MOS capacitors on 4H-SiC-
dc.typeThesis-
dc.contributor.AlternativeAuthorSuhyeong Lee-
dc.description.degreeDoctor-
dc.contributor.affiliation공과대학 재료공학부-
dc.date.awarded2018-02-
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