Circuit and Architecture Optimization Techniques for Emerging Technologies of High-Speed Computing

Abstract

For system-on-chip (SoC) design improvement in more-than-Moore scale, entirely new high-speed computing technologies beyond conventional optimizations are often proposed. They can solve many limitations of existing designs from different angle of the view. However, as engineers are not mature with such new technologies, these emerging technologies are facing many problems in realization. Even larger implementation overhead than benefits prevents these technologies from being used in real world. This dissertation presents some of the emerging high-speed computing technologies and their limitations in realization, and proposes a solution to each of the technologies to be used in industry with lower technology entry barrier. Firstly, TSV(Through-Silicon Via)-based 3-D IC is introduced for denser chip design by stacking dies vertically. In this dissertation, we solved TSV reliability problem in the clock tree of 3-D IC with a full solution of designing and synthesizing a TSV fault-tolerant 3-D clock tree. Secondly, as clock tree synthesis becomes more complicated under recent design environment of low supply voltage and large variations, asynchronous circuit design have been considered as an alternative to the clock-based synchronous design. In the dissertation, we proposed a new structure of single-rail/dual-rail hybrid asynchronous design that achieves both robustness against variations and low implementation overhead. This design is also devised to be compatible with conventional standard cell libraries and computer-aided design (CAD) tools for productivity and practicality. Lastly, with the aid of clock-less circuit design, biologically inspired neuromorphic computing architecture is emerged to overcome the memory-computation gap in the traditional von Neumann architecture. We improved the performance of the architecture with a new approach of cross optimization of multiple synapse networks in implementation of a deep neural network (DNN).