S-Space College of Engineering/Engineering Practice School (공과대학/대학원) Dept. of Electrical and Computer Engineering (전기·정보공학부) Theses (Ph.D. / Sc.D._전기·정보공학부)
Highly compact ane accurate circuit-level macro modeling of charge-trap flash memory
전하 포획형 플래시 메모리 소자에 대한 매우 간소하고 정확도 높은 회로 레벨 매크로 모델링
- 공과대학 전기·컴퓨터공학부
- Issue Date
- 서울대학교 대학원
- charge-trap flash memory; program; macro modeling; compact modeling; charge centroid; 3D CTF memory
- 학위논문 (박사)-- 서울대학교 대학원 : 공과대학 전기·컴퓨터공학부, 2018. 2. 박병국.
- Charge-trap flash (CTF) memories are considered to represent the promising alternative in order for eventually replacing the floating-gate (FG) flash memory technologies in the near future owing to its higher device scalability and are targeted by developments of the most recent three-dimensional (3D) array architectures indeed. Various device structures and charge trapping layer materials have been adopted for advancing the CTF memories and different physical mechanisms have been closely studied in the respective cell operations.
In this paper, a highly compact and accurate circuit model of CTF memory cell is proposed, in consideration of the transient behaviors for describing the program operations. Although several compact models have been reported in the previous literature, the time-dependent behaviors of CTF cell have not been precisely reflected in the past models and the discrepancy between modeling and empirical results gets worse as the operation time elapses. The proposed circuit-level macro model in this work simply consists of one transistor, one voltage-controlled capacitor (VCCAP), and one voltage-controlled current source (VCCS) where the transient behaviors are mathematically embedded, with the improved compactness by reducing the number of current sources in the previous works. For expecting higher credibility of the developed SPICE models, they are verified by the measurement results from the fabricated CTF memory devices having the silicon-oxide-nitride-oxide-silicon (SONOS) stack under various operating conditions, by which plausible agreements between modeling and measurement results are demonstrated. Our more realistic circuit-level macro model would be practical and beneficial in designing the high-density 2D and 3D memory array and system architectures for 3D CTF memory. In particular, the results in this work should be significant when more accurate prediction of rigorous management of very narrow cell threshold voltage (Vt) window is indispensable for multi-level cell (MLC) and higher-level cell (XLC) operations.