Methodology for Synthesizing Clock Spine Networks

Abstract

Clock distribution network is used to deliver a clock signal from clock source to clock sinks (flip-flops and latches) in synchronous digital systems. However, the process variation caused by the CMOS process technology scaling increases the global clock skew. This reduces the clock speed of circuits, often causing a circuit failure. Consequently, it is essential to minimize the clock skew or control the clock skew in a bound during the synthesis of clock networks. To mitigate the clock skew induced by process variation, clock mesh network is investigated. However, though the clock mesh network provides a high variation tolerance, the clock resource and power consumption on the mesh is unacceptably high. To compromise the clock resource with clock skew variation, the clock spine network can be used as an alternative. But there is not much works which addressed the clock spine network synthesis. This dissertation addresses the problem of developing a synthesis method for clock spine networks, which is able to systematically explore the clock resource and clock skew variability. The main idea is to transform the problem of allocating and placing clock spines on a plane into a slicing floorplan optimization problem, in which every candidate of clock spine network structures is uniquely expressed into a postfix notation to enable a fast cost computation in the slicing floorplan optimization. Recursive bipartition method and tolerance metric for spine networks are proposed to reduce clock resource consumption while keeping tolerance to variation of clock spine network at a certain level. In addition, to explore the various types of clock spine structure, methodology for synthesizing crossed clock spines is proposed as well. With crossed clock spine structure, clock skew, clock resource usage, and power consumption of clock networks can be controlled. Finally, a clock spine synthesis method that supports clock gating at spine level is proposed. Experimental results demonstrate that our proposed method successfully further reduces the clock skew, clock resource, and power consumption over the networks produced by the previous work.