A Novel FPGA Implementation of a Time-to-Digital Converter Supporting Run-Time Calibration

Abstract

Time-to-Digital Converter (TDC) is widely used in applications that need to measure the time interval between events. Previous designs required large area for TDC and high speed clock to compensate for process, voltage and temperature (PVT) variation while performing measurements. Several other architectures succeeded in eliminating the dependency of the reference clock and the size of TDC but cannot calibrate the TDC on-the-fly. To overcome those problems in the previous TDCs, this thesis proposes a novel design of a synthesizable TDC. The proposed TDC uses a ring oscillator to measure the interval by counting the number of cycles in the interval. As a result, the accuracy drop by the delay variation is significantly decreased. To reduce the precision drop by the measurement with the ring oscillator, an additional delay line and a secondary counter are used in the TDC. Furthermore, the proposed TDC reduces PVT variation by estimating the delay time of one buffer and measuring the speed of the ring oscillator at run-time. The proposed TDC is implemented by using Xilinx Spartan-6 LX9 FPGA with 50MHz oscillator and it achieves 19.1ps resolution.