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A High-Speed Link Transmitter for Emulating Channel Attenuation with Logarithmic and Exponential Function : 대수함수와 지수함수를 통한 전송신로 손실을 모사한 고속신호 전송회로

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dc.contributor.advisor김재하-
dc.contributor.author김경훈-
dc.date.accessioned2018-11-12T00:53:23Z-
dc.date.available2018-11-12T00:53:23Z-
dc.date.issued2018-08-
dc.identifier.other000000153127-
dc.identifier.urihttps://hdl.handle.net/10371/142981-
dc.description학위논문 (박사)-- 서울대학교 대학원 : 공과대학 전기·컴퓨터공학부, 2018. 8. 김재하.-
dc.description.abstractThis paper describes a transmitter that can emulate a wide variety of frequency-dependent loss characteristics of high-speed DRAM channels, with an aim to facilitate an automated test procedure for DRAM interface that does not require physical reconfiguration of channels. Specifically, the proposed transmitter can generate the waveform of an NRZ data stream that experienced the adjustable amounts of skin-effect loss and dielectric loss of electrical channels. To save the hardware cost of implementing a high-speed, high-resolution digital-to-analog converter, the transmitter constructs the waveform using a set of logarithmic and exponential basis functions, each of which is implemented using a pseudo-logarithmic amplifier and low-bandwidth amplifier with adjustable gain and bandwidth, respectively. The prototype chip fabricated in 65um CMOS consumes 52,000um2 and operates over 1.4~7Gbps while dissipating 38mW at 7Gbps. It is demonstrated that the implemented transmitter can emulate 10~40-long microstrip lines on FR4 material with the peak error less than 6.25% in the pulse response.-
dc.description.tableofcontentsCHAPTER 1 INTRODUCTION 1

1.1 DRAM INTERFACE. 3

1.1.1. INTERFACE OF THE COMPUTING MEMORY . 4

1.1.2. INTERFACE OF THE MOBILE MEMORY 5

1.1.3. HIGH BANDWIDTH MEMORY . 8

1.2 MEMORY TEST. 9

1.2.1. DRAM TEST SEQUENCE 10

1.3 CHANNEL TESTING ENVIRONMENT IN HIGH-SPEED SERIAL LINK . 13

CHAPTER 2 CHANNEL ATTENUATION AND MODELING 16

2.1 CHANNEL NOISE. 16

2.1.1. SKIN-EFFECT 18

2.1.2. DIELECTRIC LOSS . 20

2.1.3. PCB LOSS MECHANISM . 21

2.2 MEMORY CHANNEL CHARACTERISTICS 25

CHAPTER 3 CHANNEL-EMULATING MODEL 28

3.1 CHANNEL EQUALIZATION AND EMULATION . 30

3.1.1. DIELECTRIC EQUALIZER AND EMULATOR 40

3.1.2. SKIN-EFFECT EQUALIZER 35

3.1.3. SKIN-EFFECT EMULATOR 38

3.2 EMULATION MODEL PROPOSAL 40

CHAPTER 4 THE ARCHITECTURE OF CHANNEL-EMULATING TRANSMITTER 48

4.1 LOGARITHMIC APPROXIMATION . 49

4.1.1. PSEUDO-LOGARITHMIC APPROXIMATION 50

4.1.2. PSEUDO-LOGARITHMIC FOR DATA INPUT. 52

4.2 DIELECTRIC LOSS EMULATOR 56

4.3 EMULATING RESULTS. 57

CHAPTER 5 CIRCUIT IMPLEMENTATION 61

5.1 PROPOSED EMULATION ARCHITECTURE . 62

5.1.1. TRANSMITTER 63

5.1.2. PROGRAMMABLE SHIFT REGISTER AND SERIALIZER . 66

5.1.3. PATTERN GENERATOR 68

5.1.4. CLOCK GENERATOR 69

CHAPTER 6 EXPERIMENTAL RESULTS 73

6.1 EMULATION PROCEDURE 77

6.2 MEASUREMENT ENVIRONMENTS 78

6.3 EMULATION WITH ACTUAL CHANNELS. 84

6.4 SIMULATION WITH S-PARAMETERS 87

CHAPTER 7 CONCLUSION 88

BIBLIOGRAPHY 91

초 록 95
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dc.language.isoen-
dc.publisher서울대학교 대학원-
dc.subject.ddc621.3-
dc.titleA High-Speed Link Transmitter for Emulating Channel Attenuation with Logarithmic and Exponential Function-
dc.title.alternative대수함수와 지수함수를 통한 전송신로 손실을 모사한 고속신호 전송회로-
dc.typeThesis-
dc.contributor.AlternativeAuthorKyunghoon Kim-
dc.description.degreeDoctor-
dc.contributor.affiliation공과대학 전기·컴퓨터공학부-
dc.date.awarded2018-08-
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