Publications
Detailed Information
Studies on Resonant Clock Network Synthesis and Design Technology Co-Optimization Framework : 공진 클럭 네트워크 합성과 설계 공정 동시 최적화 프레임워크에 관한 연구
DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | 김태환 | - |
dc.contributor.author | 안세용 | - |
dc.date.accessioned | 2018-11-12T01:00:26Z | - |
dc.date.available | 2018-11-12T01:00:26Z | - |
dc.date.issued | 2018-08 | - |
dc.identifier.other | 000000151987 | - |
dc.identifier.uri | https://hdl.handle.net/10371/143282 | - |
dc.description | 학위논문 (박사)-- 서울대학교 대학원 : 공과대학 전기·컴퓨터공학부, 2018. 8. 김태환. | - |
dc.description.abstract | In modern VLSI design, there exists a tendency of integrating various com-
ponents including microprocessors, memory blocks, I/O interface and peripher- als, which can be classified into digital, analog and mixed-signal by their oper- ation. In general, digital blocks are implemented as synchronous circuits which operate in sync with the global clock signal and occupy majority portion of the total chip in terms of area and power consumption. Therefore, saving of power consumption caused by the clock network is important in achieving a low-power design. On the other hand, in development of advanced technology nodes, the sequential product development flow faces a challenge of difficulty in overall product optimization due to increased TAT (turn-around time) between design and process development. To resolve this, a DTCO (Design Technology Co-Optimization) is introduced. Impact of process development to an overall product can be predicted and analyzed through standard cells which occupy a majority of digital blocks up to 60%. First, by introducing on-chip inductors, LC resonance is adopted to reduce excessive power consumption of clock distribution network. In the presence of DVFS (Dynamic Voltage/Frequency Scaling), a widely used low power tech- nique in modern VLSI design, a methodology of synthesizing resonant clock network is proposed to achieve acceptable power reduction while minimizing area overhead of inductors and clock driving buffers. Experiments of several benchmarks show the effectiveness of the proposed method. Second, a standard cell layout generator is developed to produce cell lay- outs of which quality is comparable to industrys manually optimized one. The generator adopts advanced process technology including FinFET transistors, DP (double patterning) lithography, and complex design rules. In addition, a DTCO framework which uses the proposed standard cell generator as a core engine is developed for an effective DTCO work. By experiments using the pro- posed framework, it is shown that standard cells are generated successfully and optimization point between design and process can be explored. | - |
dc.description.tableofcontents | Abstract i
Chapter 1 Introduction 1 1.1 Synchronous Digital Logic Circuit 1 1.2 Resonant Clock Mesh 2 1.3 Standard Cell 4 1.4 Design Technology Co-Optimization 5 1.5 Contributions of This Dissertation 7 Chapter 2 Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage / Frequency Scaling 9 2.1 Introduction 9 2.2 Designs of Adjustable LC Tanks 13 2.3 DVFS-Aware Synthesis of Resonant Clock Networks 16 2.3.1 Inductor Allocation and Placement Supporting DVFS 16 2.3.2 Driving Buffer Allocation and Placement Supporting DVFS 22 2.4 Selection of Resonant Frequencies 26 2.5 Experimental Results 33 2.5.1 Comparison of RCS-DVFS with Conventional Approach LARCS 34 2.5.2 Effect of Quality Factor on Power Consumption 37 2.5.3 Effect of Transmission Gate Location on Power Consumption 39 2.5.4 Power Consumption and Area Overhead of the Design Synthesized by Selecting Resonant Frequencies 44 2.5.5 Comparison of Clock Slew Rates 47 2.5.6 Transition Time Evaluation 49 2.6 Summary 49 Chapter 3 Design Rule and Cell Architecture Co-Evaluation Framework for Design Technology Co-Optimization 51 3.1 Introduction 51 3.2 Standard Cell Layout Generator 54 3.2.1 Preliminaries 54 3.2.2 Proposed Flow of Cell Layout Generation 59 3.2.3 Techniques for Cell Layout Optimization 64 3.2.4 Experimental Results 72 3.3 DTCO Framework and DTCO Item Exploration Results 79 3.3.1 DTCO Framework Overview 79 3.3.2 DTCO Items Exploration 80 3.3.3 T2S, T2T GR Exploration with Fixed S2S GR 82 3.3.4 S2S DP Rule Exploration with Fixed S2S GR 82 3.3.5 M1 Minimum Area Rule Exploration 82 3.4 Summary 86 Chapter 4 Conclusion 87 4.1 Chapter 2 87 4.2 Chapter 3 88 초록 97 | - |
dc.language.iso | en | - |
dc.publisher | 서울대학교 대학원 | - |
dc.subject.ddc | 621.3 | - |
dc.title | Studies on Resonant Clock Network Synthesis and Design Technology Co-Optimization Framework | - |
dc.title.alternative | 공진 클럭 네트워크 합성과 설계 공정 동시 최적화 프레임워크에 관한 연구 | - |
dc.type | Thesis | - |
dc.contributor.AlternativeAuthor | Seyong Ahn | - |
dc.description.degree | Doctor | - |
dc.contributor.affiliation | 공과대학 전기·컴퓨터공학부 | - |
dc.date.awarded | 2018-08 | - |
- Appears in Collections:
Item View & Download Count
Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.