A Stacked RF Power Amplifier with Adaptive Gate Bias Controller for Envelope Tracking Using 0.32-μm SOI

Abstract

In this thesis, an envelope tracking RF power amplifier system using 0.32 μm is presented. In supply modulator, especially in linear stage, push-pull common source CMOS output stage is used for rail to rail output voltage swing. In switching stage, to reduce switching loss due to intrinsic capacitances of power transistors, voltage regulators are used. The experimental results show that, designed supply modulator successfully tracks 3.84MHz WCDMA modulated signal with very high efficiency of 87.5%. Its maximum output voltage reaches 2.8V which is about 90.3% of supply rail with 3.1V supply voltage. In RFPA, a novel bias controller for envelope tracking is demonstrated. A gate bias controller is composed of two blocks. The first is a buffer made of simple OP-AMP to short the envelope signal from drain node. From this buffer, each bias level is adaptively adjusted free from envelope coupling which can deteriorate overall performance. The second is a comparator for shorting top transistor when drain voltage is lower than a reference value. As a result, PA maintains high efficiency although typical stacked PA shows poor efficiency at low supply voltage level. The experimental results show that, this controller improves about 10% PAE at low supply voltage also shows peak PAE of 61.3% With all circuits combined, envelope tracking power amplifier system is demonstrated. Delay between RF path and envelope path is adjusted using delay line in PCB. With WCDMA modulated signal, maximum PAE is 52.3% and even in 2dB back off, PAE remains 43%. Also, in the mid power level, 3% efficiency improvement is found thanks to adaptive gate bias controller.