A STUDY ON DESIGN CONSIDERATIONS OF HIGH FREQUENCY STACKED POWER AMPLIFIER

Abstract

This paper presents a 24GHz triple stacked power amplifier using standard 0.13μm CMOS technology for automotive radar system. By stacking transistors in series, output voltage swing at output load increases without exceeding the transistor breakdown voltage limitations. Comparing with a parallel current combining method, series voltage combining method using a stacked amplifier architecture can realize the relatively a high optimum load point which improve the output matching bandwidths and less power loss in output matching network. However, at high frequencies, parasitic capacitances at the drain of each transistor become significant and it cause a phase difference between output current and voltage swing which degrades the performance of the power amplifier (PA). To solve this problem, an optimum inter-stage matching technique using inductors is introduced. With proposed optimum inter-stage matching method, a simulated power amplifier performs a gain of 13.8 dB and saturated output power of 16.2 dBm with power added efficiency (PAE) of 15.7%. But in practical design, due to the layout problems, a measured power amplifier performs unintentionally. This will be addressed in detail later on next following chapters.