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A BJT based 1T-DRAM cell having SiGe heterostructure

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Authors
심경석
Advisor
박영준
Major
전기·컴퓨터공학부
Issue Date
2012-02
Publisher
서울대학교 대학원
Abstract
As the DRAM cell shrinks, the down scaling becomes increasingly difficult in particular due to the capacitor which has become harder to scale. In order to overcome cell area scalability and process complexity issues of 1T-1C DRAM, the capacitor-less 1T-DRAM cell, based on the floating body effect, have been proposed and applied to the embedded DRAM applications.
The data is stored in capacitor in the conventional DRAM, whereas the 1T-DRAM does not need the external capacitor since the floating body effects within the transistor is utilized. The memory storage mechanism is based on the threshold voltage (Vth) shift produced by majority carrier excess (accumulation, write 1) or evacuation (depletion, write 0) in the floating body.
A recently proposed 1T-DRAM cell utilizes the parasitic BJT current in the SOI MOSFET structure for both writing and reading data. This BJT-based 1T-DRAM cell has attracted interests mainly because of its full compatibility with the standard SOI processing and its potentially excellent performance such as the high sensing margin and retention characteristics. However, due to the high voltage operation, which is necessary to induce the parasitic BJTs avalanche breakdown, it is not suitable for the low voltage operation required in the embedded memory applications and the weak dynamic retention characteristics due to disturb between the adjacent cell on memory operation is considered as the biggest disadvantages.
In this paper, we propose a BJT-based floating body 1T-DRAM cell made of a novel heterostructure suitable to low power DRAM technology. Based on the numerical simulation, we verify that the proposed structure is capable of reducing the breakdown voltage (BVCEO) and single-transistor latch (STL) bias in the BJT-based 1T-DRAM, which largely depends on the impact ionization and parasitic BJT through enhancement of the current gain (β). Moreover, it is expected that the novel structure with the SiGe has advantages in dynamic retention characteristics due to reduced bit-line (BL) disturb compared with the normal Si device. Due to the lowered drain voltage, the BL disturb effect has been reduced and the 1 disturb retention characteristics are improved accordingly over the normal Si device. By selecting the thin SiGe layer structure adequately in terms of the thickness and Ge fraction, it is possible to increase the impact ionization at low drain voltage while minimizing the effects of GIDL (Gate-induced drain leakage).
Moreover, dynamic retention characteristics of the heterostructure device are investigated with the variation of the parameters which come from the Si/SiGe interface trap properties such as trap energy level, trap density. These parameters decide the leakage current due to the trap-assisted tunneling (TAT) under 1 disturb condition (reverse-biased).
Language
eng
URI
https://hdl.handle.net/10371/156584

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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Ph.D. / Sc.D._전기·정보공학부)
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