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Bias Temperature Instability Characteristics for Hf-based Gate Dielectrics on Si and Ge substrates
실리콘과 게르마늄 기판 위에서 Hf 기반 게이트 산화막의 Bias Temperature Instability 특성

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Authors
정형석
Advisor
황철성
Major
협동과정 나노과학기술전공
Issue Date
2012-02
Publisher
서울대학교 대학원
Abstract
As the gate length of complementary metal oxide semiconductor field effect transistors (CMOSFETs) continues to shrink, the continuous scaling down of SiO2 gate dielectrics is reaching its physical limit due to the high leakage current and reliability concerns. Hf-based gate dielectrics are considered to be the most promising candidates for replacing SiO2 gate dielectrics. Recently, Hf-based gate dielectrics with a metal gate have been already implemented in a mass production.
The bias temperature instability (BTI) characteristics of conventional nitrided SiO2 gate dielectrics are a major reliability concern in current CMOS technology. The introduction of Hf-based gate dielectrics causes further complications in BTI characteristics because Hf-based oxides contain a much larger amount of pre-existing defects than nitrided SiO2. The presence of high density of defects in Hf-based oxides requires to understand the degradation mechanism of BTI characteristics.
Firstly, the nMOS PBTI and pMOS NBTI characteristics of HfO2 gate dielectrics were investigated. The interface trap charge (∆Nit) and bulk oxide trap charge (∆Not) densities were estimated separately to determine the defects responsible for the threshold voltage (Vth) shift during the BTI stress. The contribution of ∆Nit to the Vth shift for nMOS PBTI and pMOS NBTI were ~ 5% and ~ 30%, respectively. Therefore, it is believed that the main degradation mechanism of nMOS PBTI is related to the generation of oxide trap charges. However, the degradation under pMOS NBTI stress is due to the generation of both interface states and oxide trap charges.
In order to improve the electrical and reliability properties of HfO2, either Nitrogen or Zr is incorporated into HfO2 gate dielectrics. First, the effects of Zr composition on the crystallization behaviors and reliability characteristics of Hf1-xZrxOy gate dielectric films were examined. ZrO2 showed a much smaller Vth shift under the positive bias stress compared to the HfO2. In addition, as the Zr composition in the Hf1-xZrxOy films increased, the reduction of crystallization temperature and the transformation from monoclinic phase to tetragonal were observed. The grain size of the crystallized ZrO2 film is much smaller than that of crystallized HfO2. The flat band voltage (Vfb) shift under positive gate bias stress in p-type MOS capacitor (pMOSCAP) devices show a similar trend to the Vth shift in nMOSFET devices. In addition, the annealed ZrO2 films show a large reduction of Vfb shift under the positive bias stress compared to the as-deposited ZrO2 in pMOSCAP devices. The improved bias temperature instability characteristics of ZrO2 compared to HfO2 is related to the smaller grain size of crystallized ZrO2.
Second, when Nitrogen (~17%) is incorporated into HfO2, the dramatic reduction of capacitance equivalent oxide thickness value and increase of leakage current were observed. In addition, the nitrogen incorporated HfOxNy film shows turn-around effect under the positive gate stress bias in nMOSFET. The threshold voltage (Vth) shifts to the positive direction during the initial one sec due to the pre-existing trap sites in Hf-based gate dielectrics. Subsequently, Vth shifts to the negative direction due to hole trapping, originated from the generation of electron-hole pairs related to the surface plasmon.
Ge is one of the potential candidates for channel material in future CMOS devices due to its higher electron (x2) and hole (x4) mobility compared to Si. However, several challenges have to be overcome to implement Ge into a fully CMOS-compatible process. One of the critical issues for Ge integration is the formation of the unstable Ge oxide, which causes the degradation of electrical properties such as increase of interface states and large capacitance- voltage (C-V) hysteresis. Large C-V hysteresis of atomic layer deposited (ALD) HfO2 on Ge substrate can dramatically reduce by decrease deposition temperature from 280oC to 200oC. The reduction of C-V hysteresis can be explained by the less generation of Ge oxide at the interface between HfO2 and Ge substrate by reducing deposition temperatures. Finally, 200oC deposited HfO2 film (200 oC-HfO2) shows less Vfb shift under the negative stress bias compared to 280oC deposited HfO2 (280 oC-HfO2). In addition, the effect of the carbon concentration on the crystalline phase and dielectric constant of atomic layer deposited HfO2 films was also investigated. After annealing, 200 oC-HfO2 and 280 oC-HfO2 were crystallized to the tetragonal (t) and monoclinic (m) phases, respectively. First principle calculations suggest the different crystalline phase is related to the carbon concentration within the films. C-V measurements showed that crystallized 280 oC-HfO2 (m-HfO2) and amorphous 280 oC-HfO2 had a similar dielectric constant, while the crystallized 200 oC-HfO2 (t-HfO2) showed a higher dielectric constant than amorphous 200 oC-HfO2. Finally, the electrical properties of HfO2 on Ge substrate were investigated after inserting various passivation interfacial layers (PILs) such as SiOxNy, AlOxNy, HfOxNy and LaOxNy prepared by ALD between HfO2 and Ge substrate. The larger C-V hysteresis of the HfO2 films grown on Ge substrate was not improved from inserting HfOxNy and LaOxNy PILs, while SiOxNy and AlOxNy PIL caused the dramatic reduction of C-V hysteresis. Finally, HfO2/SiOxNy/Ge stacks showed the comparable C-V hysteresis and charge trapping properties to HfO2/Si stacks.
Language
eng
URI
https://hdl.handle.net/10371/156737

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College of Engineering/Engineering Practice School (공과대학/대학원)Nano-Science and Technology (협동과정 나노과학·기술전공)Theses (Ph.D. / Sc.D._협동과정 나노과학·기술전공)
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