Room-temperature Operation of Poly-silicon Quantum Dot Single Electron Transistors

Abstract

Recently, a single electron transistor (SET) is considered to be a candidate for an element of a future low power, high-density integrated circuit because of a possible ultralow power operation with a few electrons. For the practical application, it is indispensable for the SET to be operated at room temperature. For this purpose, the size of the island of SET must be as small as sub-10 nm to reduce the total capacitance of SET and to overcome the problems of the thermal fluctuation. However, the size of sub-10 nm is out of the range of the present conventional micro-fabrication process. In this dissertation, for operation of single-electron transistors (SETs) at room temperature, we proposed a fabrication method for a SET with a self-aligned quantum dot by using electron beam lithography. In the introduction, the issues of complementary metal oxide semiconductor (CMOS) transistors are reviewed. Next, the basic operation principle of SET is described. Then, conventional SETs are analyzed and classified. Through the numerical simulation with a SET simulation tool, electrical characterization of device is carried out. In addition, etch-back process is investigated using various lines. Based on the simulation results and the etch-back process results, the self-aligned quantum dot single electron transistor is fabricated and its electrical characteristics are measured and analyzed. Moreover, a modified device with a hard oxide mask layer is compared to the previous version of the device through the SET simulation. To decrease the leakage current and to control the gate capacitance, the hard oxide mask is used. Also, a chemical mechanical polishing (CMP) process is investigated for highly accurate planarization. Selective etching of a silicon nanowire on a planarized surface is formed. Finally, device properties are characterized from the measurement results. By forming a hard mask layer, gate capacitance is effectively reduced. In addition, from the parameters of the device, various kinds of applications are proposed and simulated for the self-aligned single electron transistor.