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블록 캐시와 클록 게이팅을 이용한 H.264/AVC Baseline 디코더의 저전력 설계 : The low power design for an H.264/AVC baseline decoder using block caches and clock gating

DC Field Value Language
dc.contributor.advisor이혁재-
dc.contributor.author김제선-
dc.date.accessioned2019-07-10T04:13:20Z-
dc.date.available2019-07-10T04:13:20Z-
dc.date.issued2011-02-
dc.identifier.other000000029010-
dc.identifier.urihttps://hdl.handle.net/10371/158997-
dc.identifier.urihttp://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000029010ko_KR
dc.description학위논문 (박사)-- 서울대학교 대학원 : 전기. 컴퓨터공학부, 2011.2. 이혁재.-
dc.format.extentviii, 98 p.-
dc.language.isokor-
dc.publisher서울대학교 대학원-
dc.subjectH.264 AVC-
dc.subject저전력 설계-
dc.subject블록 캐시-
dc.subject프레임 메모리 압축-
dc.subject모듈 수준 클록 게이팅-
dc.subjectlow power design-
dc.subjectblock cache-
dc.subjectframe memory compression-
dc.subjectmodule-based clock gating-
dc.title블록 캐시와 클록 게이팅을 이용한 H.264/AVC Baseline 디코더의 저전력 설계-
dc.title.alternativeThe low power design for an H.264/AVC baseline decoder using block caches and clock gating-
dc.typeThesis-
dc.typeDissertation-
dc.description.degreeDoctor-
dc.contributor.affiliation전기. 컴퓨터공학부-
dc.date.awarded2011-02-
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