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(A) study on clock generation circuit using multiphase delay-locked-loop : 다중 위상 지연동기루프를 이용한 클록 발생 회로에 관한 연구
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 정덕균 | - |
| dc.contributor.author | 송호영 | - |
| dc.date.accessioned | 2019-07-10T04:22:48Z | - |
| dc.date.available | 2019-07-10T04:22:48Z | - |
| dc.date.issued | 2011-02 | - |
| dc.identifier.other | 000000029042 | - |
| dc.identifier.uri | https://hdl.handle.net/10371/159084 | - |
| dc.identifier.uri | http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000029042 | ko_KR |
| dc.description | 학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2011.2. 정덕균. | - |
| dc.format.extent | x, 104장 | - |
| dc.language.iso | eng | - |
| dc.publisher | 서울대학교 대학원 | - |
| dc.subject | multiphase DLL | - |
| dc.subject | clock generator | - |
| dc.subject | dual-input interpolating delay | - |
| dc.subject | bang-bang phase detector | - |
| dc.subject | skew calibration | - |
| dc.title | (A) study on clock generation circuit using multiphase delay-locked-loop | - |
| dc.title.alternative | 다중 위상 지연동기루프를 이용한 클록 발생 회로에 관한 연구 | - |
| dc.type | Thesis | - |
| dc.type | Dissertation | - |
| dc.description.degree | Doctor | - |
| dc.contributor.affiliation | 전기·컴퓨터공학부 | - |
| dc.date.awarded | 2011-02 | - |
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