Analysis of Self Heating Effects in Nanoplate FET and 3D NAND Flash Memory

Abstract

In this thesis, self-heating effects (SHEs) in three-stacked nanoplate FETs were investigated majorly through the TCAD simulation over various logic device nodes. In order to obtain high reliability, the evaluation of SHEs was performed after accurate IDVG curve fitting based on the experimental data in the total research. First, general analysis on SHEs was conducted to confirm the influence of SHEs to electrical characteristics. The optimized nanoplate width for great electrical properties was proposed by using the figure-of-merit factor under the consideration of SHEs. In addition, difference of heat flux between FinFET and stacked nanoplate FET was analyzed. More quantitatively, the overall performance of a stacked nanoplate FET was analyzed as a candidate for a 3.5-nm node. In order to conduct this analysis, Monte Carlo (MC) simulation was used to obtain near-realistic data and 3D TCAD simulation data were fitted under the consideration of strain engineering. Through this process, the characteristics of the stacked nanoplate FET were analyzed in terms of structure optimization. In addition, strain effect, as one of the mechanical effects, to enhance the performance for nanoplate FET was included in the fitted data. Therefore, the way in which ON-current (Ion) increased by strain engineering influences SHEs was investigated, and appropriate strain engineering to obtain the best performance was proposed. For more scaling node, the optimum geometry specification was proposed through comparison of RC delay from previous studies. Additionally, the impacts of self-heating effects in the 3-nm node were evaluated with the above similar way. The degradation by SHEs was verified in a single device and in ring oscillator (RO) operation. pMOS is comparatively stronger than nMOS in terms of SHEs due to wider channel width. In RO operation, the influence of SHEs begins to appear at over 0.65 V through power and speed comparison. Moreover, the evaluation of SHEs in 3D NAND (vertical NAND) was performed through TCAD simulation. To obtain accurate results, the thermal conditions for SHEs were proposed based on the experimental data as well. After that, the lattice temperature distribution in 3D NAND was investigated. Transient simulation was also conducted to confirm the change of SHEs over time. With increasing the number of layers in 3D NAND, the difficulty of heat conduction was observed. By using thermal time constant in 3D NAND, SHEs depending on the number of layers were investigated. Additionally, two types of 3D NAND, gate-all-around (GAA) macaroni and single-gate vertical channel (SGVC) flat cells were compared in terms of SHEs. As a representative problem by SHEs, Vt variation was analyzed.

본 논문에서는, 다양한 Logic device의 TCAD 시뮬레이션을 통해 3단 적층형 nanoplate FET의 self heating effects (SHEs)를 주로 연구하였다. 시뮬레이션의 신뢰도를 위해, SHE 결과분석은 실험 데이터에 근거한 정확한 IGVG fitting 이후에 수행되었다. 그 후에 SHE에 대한 분석을 수행하여 SHE가 전기적 특성에 미치는 영향을 연구하였다. 더 세밀하게는 nanoplate FET의 성능을 3.5nm 노드의 후보로 분석하였다. 이 분석을 실시하기 위해, 거의 실제에 가까운 데이터를 얻기 위해 몬테카를로(MC) 시뮬레이션을 사용하였고, 이를 3D TCAD 시뮬레이션 데이터에 이식하여 시간 효율을 증가시켰다. 이를 통해 nanoplate FET의 특성을 SHEs 를 줄이기 위한 구조 최적화 차원에서 분석했다. 또한 Strain engineering이 연구에 포함되어 SHE에 의해 전류가 어떻게 변화하는지를 연구하였다. 더 작은 scaling에서는, 이전 연구와 비교한 RC 지연을 통해 규격이 제안되었다. SHE에 의한 성능 감소는 단일 장치와 Ring oscillator (RO) 연구를 통해 검증되었다. pMOS는 채널 폭이 넓어 SHE 면에서는 nMOS보다 더 강한 특성을 보인다. RO에서 SHE의 영향은 전력 및 속도 비교를 통해 0.65V 가 효율적으로 나타났다. 추가적으로 3D NAND(수직 NAND)에서의 SHE 연구는 TCAD 시뮬레이션을 통해 이루어졌다. 정확한 결과를 얻기 위해 실험 데이터에 기초하여 SHE의 thermal boundary condition을 제안하였다. 그 후, 3D NAND의 격자 온도 분포를 조사하였다. 시간 경과에 따른 SHE의 변화를 확인하기 위해 transient simulation 또한 실시했다. 3D NAND의 층 수가 증가함에 따라 열전도 특성이 관측되었다. 3D NAND에서 thermal time constant를 사용하여 층 수에 따라 SHE를 조사하였다. 또한 SHE 측면에서 3D NAND, gate-all-around (GAA) macaroni, single-gate vertical channel (SGVC)를 비교하였다. SHE의 대표적인 문제로 Vt 변동을 제시되었다.