Charge transport and morphology of pentacene films confined in nano-patterned region

Abstract

The transport and morphology of macroscopic organic transistors have been thoroughly explained. However, the relationship between charge transport and the morphology of organic semiconductors in nano-confined regions is not well understood, which is required to design high-performance nano-electronics. Therefore, in this study, the electrical performance of pentacene thin-film transistors (TFTs) fabricated on nano-scale confined geometries was compared with that of other TFT systems fabricated on micro-scale confined or flat dielectrics. The results showed that the photoresist (PR) reliefs patterned onto silicon dioxide (SiO2) dielectrics could control the growth mode of pentacene in the confined regions. As the line spacing between the PR patterns decreased to below the average size of pentacene normally grown on SiO2 dielectrics (similar to 1.7 mu m), field-effect mobility (mu(FET)) of pentacene TFTs improved considerably. Specifically, the mu(FET) values for the 250 nm patterned dielectric system were as high as 0.33 cm(2) V-1 s(-1), which was greater than those of the wider-patterned PR or flat dielectric systems (<= 0.15 cm(2) V-1 s(-1)). These findings were related to the enhancement of charge-carrier transport owing to the anisotropic pi-conjugated crystals nucleated from the nano-confined edges, providing important information that can be used in the design of high-performance nano-scale organic electronics.