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System Architecture Directions for Post-SoC/32-bit Networked Sensors
Cited 20 time in
Web of Science
Cited 28 time in Scopus
- Authors
- Issue Date
- 2018
- Publisher
- ASSOC COMPUTING MACHINERY
- Citation
- SENSYS'18: PROCEEDINGS OF THE 16TH CONFERENCE ON EMBEDDED NETWORKED SENSOR SYSTEMS, pp.264-277
- Abstract
- The emergence of low-power 32-bit Systems-on-Chip (SoCs), which integrate a 32-bit MCU, radio, and flash, presents an opportunity to re-examine design points and trade-offs at all levels of the system architecture of networked sensors. To this end, we develop a post-SoC/32-bit design point called Hamilton, showing that using integrated components enables a similar to$7 core and shifts hardware modularity to design time. We study the interaction between hardware and embedded operating systems, identifying that (1) post-SoC motes provide lower idle current (5.9 mu A) than traditional 16-bit motes, (2) 32-bit MCUs are a major energy consumer (e.g., tick increases idle current > 50 times), comparable to radios, and (3) thread-based concurrency is viable, requiring only 8.3 mu s of context switch time. We design a system architecture, based on a tickless multithreading operating system, with cooperative/adaptive clocking, advanced sensor abstraction, and preemptive packet processing. Its efficient MCU control improves concurrency with similar to 30% less energy consumption. Together, these developments set the system architecture for networked sensors in a new direction.
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