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Partial bus-invert coding for power optimization of system-level bus
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Shin, Youngsoo | - |
dc.contributor.author | Chae, Soo-Ik | - |
dc.contributor.author | Choi, Kiyoung | - |
dc.date.accessioned | 2009-12-17T04:38:31Z | - |
dc.date.available | 2009-12-17T04:38:31Z | - |
dc.date.issued | 1998 | - |
dc.identifier.citation | International Symposium on Low Power Electronics and Design 1998, August 10-12, pp.127-132 | en |
dc.identifier.uri | https://hdl.handle.net/10371/21153 | - |
dc.description.abstract | We presen t a partial bus-in vertcoding scheme for power
optim ization of system level bus. In the proposed scheme, we select a su b-group of bus lines in volv ed in b us enciondg to avoid unnecessary inversion of b us lines not in the sub - group thereby redu cing th e total n um ber of bus tran sitions. We propose a heuristic algorithm that selects the sub-grou p of bus lines for b us encodin g. Ex periments on benchmark examples in dicate that the partial bus-in vert coding reduces the tot al bus transitions b y 62.6% on the average, compared to that of the unencoded patterns. | en |
dc.description.sponsorship | The authors would like to thank Seokjun Lee and Prof.
Wonyong Sung of Seoul National University for providing us example patterns of an audio decoder. | en |
dc.language.iso | en | - |
dc.publisher | International Symposium on Low Power Electronics and Design | en |
dc.title | Partial bus-invert coding for power optimization of system-level bus | en |
dc.type | Conference Paper | en |
dc.contributor.AlternativeAuthor | 신영수 | - |
dc.contributor.AlternativeAuthor | 채수익 | - |
dc.contributor.AlternativeAuthor | 최기영 | - |
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