서울대학교 중앙도서관

S-Space 소개

My S-Space

로그인이 필요합니다.

Login

S-Space

Browse

Author

Jump to a point in the index

Or type in a year

Sort by
In order
Results/Page
Authors/record

Showing results 1 to 15 of 15

Issue Date	Title / Author(s) / Citation	File	Altmetrics
2014-06	A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with-106dBc/Hz In-band noise using time amplifier based TDC Elkholy, Ahmed; Anand, Tejasvi; Choi, Woo Seok; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Symposium on VLSI Circuits, Digest of Technical Papers, p. 6858391	DOI
2014-06	A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement Nandwana, Romesh Kumar; Anand, Tejasvi; Saxena, Saurabh; Kim, Seong-Joong; Talegaonkar, Mrunmay; Elkholy, Ahmed; Choi, Woo-Seok; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Symposium on VLSI Circuits, Digest of Technical Papers, p. 6858446	DOI
2015-04	A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method Nandwana, Romesh Kumar; Anand, Tejasvi; Saxena, Saurabh; Kim, Seong-Joong; Talegaonkar, Mrunmay; Elkholy, Ahmed; Choi, Woo Seok; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.50 No.4, pp.882-895	DOI
2015-04	A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC Elkholy, Ahmed; Anand, Tejasvi; Choi, Woo Seok; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.50 No.4, pp.867-881	DOI
2015-08	A 2.8mW/Gb/s 14Gb/s Serial Link Transceiver in 65nm CMOS Saxena, Saurabh; Shu, Guanghua; Nandwana, Romesh Kumar; Talegaonkar, Mrunmay; Elkholy, Ahmed; Anand, Tejasvi; Kim, Seong Joong; Choi, Woo Seok; Hanumolu, Pavan Kumar IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp.C352-C353	DOI
2016-02	A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b Source Synchronous Transceiver Using DVFS and Rapid On/Off in 65nm CMOS Shu, Guanghua; Choi, Woo Seok; Saxena, Saurabh; Kim, Seong-Joong; Talegaonkar, Mrunmay; Nandwana, Romesh; Elkholy, Ahmed; Wei, Da; Nandi, Timir; Hanumolu, Pavan Kumar Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.59, pp.398-U558
2016-02	A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition Shu, Guanghua; Choi, Woo Seok; Saxena, Saurabh; Talegaonkar, Mrunmay; Anand, Tejasvi; Elkholy, Ahmed; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.51 No.2, pp.428-439	DOI
2017-02	A 3-to-10Gb/s 5.75pJ/b Transceiver with Flexible Clocking in 65nm CMOS Nandwana, Romesh Kumar; Saxena, Saurabh; Elkholy, Ahmed; Talegaonkar, Mrunmay; Zhu, Junheng; Choi, Woo Seok; Elmallah, Ahmed; Hanumolu, Pavan Kumar Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.60, pp.492-493	DOI
2017-05	A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver Saxena, Saurabh; Shu, Guanghua; Nandwana, Romesh Kumar; Talegaonkar, Mrunmay; Elkholy, Ahmed; Anand, Tejasvi; Choi, Woo Seok; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.52 No.5, pp.1399-1411	DOI
2017-05	A 45-75MHz 197-452μW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS Zhu, Junheng; Mahalley, Makrand; Shu, Guanghua; Choi, Woo Seok; Nandwana, Romesh Kumar; Elkholy, Ahmed; Sahoo, Bibhudatta; Hanumolu, Pavan Kumar Proceedings of the Custom Integrated Circuits Conference, Vol.2017-April, p. 7993679	DOI
2017-09	A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS Talegaonkar, Mrunmay; Anand, Tejasvi; Elkholy, Ahmed; Elshazly, Amr; Nandwana, Romesh Kumar; Saxena, Saurabh; Young, Brian; Choi, Woo Seok; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.52 No.9, pp.2306-2320	DOI
2018-04	A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS Elmallah, Ahmed; Ahmed, Mostafa Gamal; Elkholy, Ahmed; Choi, Woo Seok; Hanumolu, Pavan Kumar 2018 IEEE Custom Integrated Circuits Conference, CICC 2018, pp.1-4	DOI
2018-05	A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR Kim, Dongwook; Choi, Woo Seok; Elkholy, Ahmed; Kenney, Jack; Hanumolu, Pavan Kumar 2018 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), pp.1-4
2019-03	A 15-Gb/s Sub-Baud-Rate Digital CDR Kim, Dongwook; Choi, Woo Seok; Elkholy, Ahmed; Kenney, Jack; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.54 No.3, pp.685-695	DOI
2020-08	A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS Kim, Dongwook; Ahmed, Mostafa G.; Choi, Woo-Seok; Elkholy, Ahmed; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.55 No.8, pp.2196-2205	DOI

1