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An auto-ranging clock recovery circuit for multi-rate systems : 다중 테이터 전송 시스템을 위한 속도 적응형 클럭 복원 회로

DC Field Value Language
dc.contributor.advisor김원찬-
dc.contributor.author박준배-
dc.date.accessioned2010-01-15T04:22:03Z-
dc.date.available2010-01-15T04:22:03Z-
dc.date.copyright2000.-
dc.date.issued2000-
dc.identifier.urihttp://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000069874eng
dc.identifier.urihttps://hdl.handle.net/10371/30894-
dc.descriptionThesis (doctoral)--서울대학교 대학원 :전기공학부,2000.en
dc.format.extentx, 95 p.en
dc.language.isoenen
dc.publisher서울대학교 대학원en
dc.subjectSerial data communicationen
dc.subjectPLLen
dc.subjectSONETen
dc.subjectclock recoveryen
dc.subjectATMen
dc.subjectPhase detectoren
dc.subjectNRZen
dc.subjectVCOen
dc.titleAn auto-ranging clock recovery circuit for multi-rate systemsen
dc.title.alternative다중 테이터 전송 시스템을 위한 속도 적응형 클럭 복원 회로-
dc.typeThesis-
dc.contributor.department전기공학부-
dc.description.degreeDoctoren
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