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High-level synthesis of partitioned bus architecture : 분할 버스 아키텍처의 상위 수준 합성

DC Field Value Language
dc.contributor.advisor최기영-
dc.contributor.author김용주-
dc.date.accessioned2010-01-15T04:22:21Z-
dc.date.available2010-01-15T04:22:21Z-
dc.date.copyright2000.-
dc.date.issued2000-
dc.identifier.urihttp://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000069760eng
dc.identifier.urihttps://hdl.handle.net/10371/30901-
dc.descriptionThesis (doctoral)--서울대학교 대학원 :전기공학부,2000.en
dc.format.extentvii, 76 p.en
dc.language.isoenen
dc.publisher서울대학교 대학원en
dc.subjectHigh-level synthesisen
dc.subjectpartitioned bus architectureen
dc.subjectDesign Space Explorationen
dc.subjectGenetic Algorithmen
dc.subjectWordlength Optimizationen
dc.titleHigh-level synthesis of partitioned bus architectureen
dc.title.alternative분할 버스 아키텍처의 상위 수준 합성-
dc.typeThesis-
dc.contributor.department전기공학부-
dc.description.degreeDoctoren
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