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Design of an All-Digital Delay-Locked Loop using a Successive Approximation Register : 연속 근사 레지스터를 이용한 All-Digital Delay-Locked Loop의 설계
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 정덕균 | - |
| dc.contributor.author | Guillaume, Weill | - |
| dc.date.accessioned | 2010-01-26T06:12:54Z | - |
| dc.date.available | 2010-01-26T06:12:54Z | - |
| dc.date.copyright | 2009. | - |
| dc.date.issued | 2009 | - |
| dc.identifier.uri | http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000037111 | eng |
| dc.identifier.uri | https://hdl.handle.net/10371/44694 | - |
| dc.description | Thesis(masters) --서울대학교 대학원 :전기. 컴퓨터공학부, 2009.2. | en |
| dc.format.extent | vii, 65 leaves | en |
| dc.language.iso | en | en |
| dc.publisher | 서울대학교 대학원 | en |
| dc.subject | All-digital | en |
| dc.subject | Delay-locked loop | en |
| dc.subject | Clock management | en |
| dc.subject | Digitalization | en |
| dc.subject | Duty-cycle correction | en |
| dc.title | Design of an All-Digital Delay-Locked Loop using a Successive Approximation Register | en |
| dc.title.alternative | 연속 근사 레지스터를 이용한 All-Digital Delay-Locked Loop의 설계 | en |
| dc.type | Thesis | - |
| dc.contributor.department | 전기. 컴퓨터공학부 | - |
| dc.description.degree | Master | en |
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