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리세스 채널을 가지는 듀얼게이트 단전자 트랜지스터의 공정 방법 : Fabrication process of recessed channel dual gate-single electron transistor
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 이종덕 | - |
| dc.contributor.author | 박상혁 | - |
| dc.date.accessioned | 2010-01-26T06:16:42Z | - |
| dc.date.available | 2010-01-26T06:16:42Z | - |
| dc.date.copyright | 2009. | - |
| dc.date.issued | 2009 | - |
| dc.identifier.uri | http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000037026 | kog |
| dc.identifier.uri | https://hdl.handle.net/10371/44776 | - |
| dc.description | 학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부, 2009.2. | ko |
| dc.format.extent | iii, 80장 | ko |
| dc.language.iso | ko | ko |
| dc.publisher | 서울대학교 대학원 | ko |
| dc.subject | Single Electron Transistor | ko |
| dc.subject | Single Electron Transistor | ko |
| dc.subject | recessed channel | ko |
| dc.subject | recessed channel | ko |
| dc.subject | dual gate | ko |
| dc.subject | dual gate | ko |
| dc.subject | self-align | ko |
| dc.subject | self-align | ko |
| dc.subject | parasitic MOSFET 억제 | ko |
| dc.subject | parasitic MOSFET suppression | ko |
| dc.subject | 공정 방법 | ko |
| dc.subject | fabrication process | ko |
| dc.subject | 상온 동작 | ko |
| dc.subject | room temperature operation | ko |
| dc.title | 리세스 채널을 가지는 듀얼게이트 단전자 트랜지스터의 공정 방법 | ko |
| dc.title.alternative | Fabrication process of recessed channel dual gate-single electron transistor | ko |
| dc.type | Thesis | - |
| dc.contributor.department | 전기. 컴퓨터공학부 | - |
| dc.description.degree | Master | ko |
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