Low-jitter design techniques of fractional-N frequency systhesizers using multi-phase clocks

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Low-jitter design techniques of fractional-N frequency systhesizers using multi-phase clocks : 다중위상 클럭을 이용한 저 잡음 주파수 합성기의 설계

DC Field	Value	Language
dc.contributor.advisor	정덕균	-
dc.contributor.author	이형록	-
dc.date.accessioned	2010-01-27	-
dc.date.available	2010-01-27	-
dc.date.copyright	2006.	-
dc.date.issued	2006	-
dc.identifier.uri	http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000046580	eng
dc.identifier.uri	https://hdl.handle.net/10371/45366	-
dc.description	Thesis(doctoral)--서울대학교 대학원 :전기·컴퓨터공학부,2006.	en
dc.format.extent	x, 117 leaves	en
dc.language.iso	en	en
dc.publisher	서울대학교 대학원	en
dc.subject	Phase-locked loop (PLL)	en
dc.subject	Phase-locked loop (PLL)	en
dc.subject	all digital PLL (ADPLL)	en
dc.subject	all digital PLL (ADPLL)	en
dc.subject	hybrid PLL	en
dc.subject	hybrid PLL	en
dc.subject	fractional-N	en
dc.subject	fractional-N	en
dc.subject	EMI	en
dc.subject	EMI	en
dc.subject	spread spectrum clocking (SSC)	en
dc.subject	spread spectrum clocking (SSC)	en
dc.subject	multiphase clock	en
dc.subject	multiphase clock	en
dc.subject	ΔΣ modulator	en
dc.subject	ΔΣ modulator	en
dc.subject	digitally controlled oscillator (DCO).	en
dc.subject	digitally controlled oscillator (DCO).	en
dc.title	Low-jitter design techniques of fractional-N frequency systhesizers using multi-phase clocks	en
dc.title.alternative	다중위상 클럭을 이용한 저 잡음 주파수 합성기의 설계	en
dc.type	Thesis	-
dc.contributor.department	전기·컴퓨터공학부	-
dc.description.degree	Doctor	en

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