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Design of transceiver with digital deskew algorithm for high-speed data communication : 디지털 스큐 감소 알고리즘을 갖는 고속 데이터 통신용 송수신기의 설계
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 김원찬 | - |
| dc.contributor.author | 최영돈 | - |
| dc.date.accessioned | 2010-01-27 | - |
| dc.date.available | 2010-01-27 | - |
| dc.date.copyright | 2005. | - |
| dc.date.issued | 2005 | - |
| dc.identifier.uri | http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000052347 | kog |
| dc.identifier.uri | https://hdl.handle.net/10371/45384 | - |
| dc.description | Thesis(doctor`s)--서울대학교 대학원 :전기·컴퓨터공학부,2005. | ko |
| dc.format.extent | xi, 112 leaves | ko |
| dc.language.iso | ko | ko |
| dc.publisher | 서울대학교 대학원 | ko |
| dc.subject | 평판 디스플레이용 송신기와 수신기 | ko |
| dc.subject | flat panel display (FPD) link | ko |
| dc.subject | LVDS | ko |
| dc.subject | LVDS | ko |
| dc.subject | UXGA | ko |
| dc.subject | UXGA | ko |
| dc.subject | 클럭 네트워크 | ko |
| dc.subject | clock network | ko |
| dc.subject | 스큐 감소알고리즘 | ko |
| dc.subject | deskew algorithm | ko |
| dc.subject | 지터 확률분포 | ko |
| dc.subject | jitter PDF | ko |
| dc.subject | DLL | ko |
| dc.subject | delay-locked loop (DLL) | ko |
| dc.subject | 주파수 판별 | ko |
| dc.subject | frequency detection | ko |
| dc.title | Design of transceiver with digital deskew algorithm for high-speed data communication | ko |
| dc.title.alternative | 디지털 스큐 감소 알고리즘을 갖는 고속 데이터 통신용 송수신기의 설계 | ko |
| dc.type | Thesis | - |
| dc.contributor.department | 전기·컴퓨터공학부 | - |
| dc.description.degree | Doctor | ko |
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