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Clock generation circuit with all-digital PLL
디지털 PLL을 이용한 clock 발생용 회로에 관한 연구

DC Field Value Language
dc.contributor.advisor정덕균-
dc.contributor.author안현석-
dc.date.accessioned2010-02-09-
dc.date.available2010-02-09-
dc.date.copyright2007.-
dc.date.issued2007-
dc.identifier.urihttp://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000043911kog
dc.identifier.urihttp://hdl.handle.net/10371/52469-
dc.description학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2007.ko
dc.format.extentii, 54 장ko
dc.language.isokoko
dc.publisher서울대학교 대학원ko
dc.subjectAll -digital PLL(ADPLL)ko
dc.subjectAll -digital PLLko
dc.subjectDCO(Digitally Controlled Oscillator)ko
dc.subjectDigitally Controlled Oscillatorko
dc.subjectTDC(Time-to-Digital Converter)ko
dc.subjectTime-to-Digital Converterko
dc.subjectDelta-Sigma Modulatorko
dc.subjectDelta-Sigma Modulatorko
dc.subject위상잡음ko
dc.subjectPhase noiseko
dc.subjectJitterko
dc.titleClock generation circuit with all-digital PLLko
dc.title.alternative디지털 PLL을 이용한 clock 발생용 회로에 관한 연구ko
dc.typeThesis-
dc.contributor.department전기. 컴퓨터공학부-
dc.description.degreeMasterko
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Master's Degree_전기·정보공학부)
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