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저전력을 고려한 재구성형 프로세싱 시스템의 최적화 : Power-conscious optimization of coarse-grained reconfigurable architecture
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 최기영 | - |
| dc.contributor.author | 박일현 | - |
| dc.date.accessioned | 2010-02-09 | - |
| dc.date.available | 2010-02-09 | - |
| dc.date.copyright | 2007. | - |
| dc.date.issued | 2007 | - |
| dc.identifier.uri | http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000043897 | kog |
| dc.identifier.uri | https://hdl.handle.net/10371/52514 | - |
| dc.description | 학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2007. | ko |
| dc.format.extent | 45 장 | ko |
| dc.language.iso | ko | ko |
| dc.publisher | 서울대학교 대학원 | ko |
| dc.subject | 시스템 온 칩 | ko |
| dc.subject | System-on-Chip (SoC) | ko |
| dc.subject | 저전력 | ko |
| dc.subject | Low Power | ko |
| dc.subject | 재구성형 프로세싱 시스템 | ko |
| dc.subject | Coarse-Grained Reconfigurable Architecture (CGRA) | ko |
| dc.subject | 콘피규레이션 캐시 | ko |
| dc.subject | Configuration Cache | ko |
| dc.subject | 루프 파이프라이닝 | ko |
| dc.subject | Loop Pipelining | ko |
| dc.subject | Context Pipelining | ko |
| dc.subject | Context Pipelining | ko |
| dc.subject | Temporal 매핑 | ko |
| dc.subject | Temporal Mapping | ko |
| dc.subject | Spatial 매핑 | ko |
| dc.subject | Spatial Mapping | ko |
| dc.subject | Processing Element | ko |
| dc.subject | Processing Element | ko |
| dc.title | 저전력을 고려한 재구성형 프로세싱 시스템의 최적화 | ko |
| dc.title.alternative | Power-conscious optimization of coarse-grained reconfigurable architecture | ko |
| dc.type | Thesis | - |
| dc.contributor.department | 전기. 컴퓨터공학부 | - |
| dc.description.degree | Master | ko |
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