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PVASiO₂ 이중 게이트 절연막을 이용한 저 이력현상의 유기 박막 트랜지스터 연구
Low hysteresis organic thin-film transistors using PVASiO₂ double layer gate dielectric

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Authors
박동욱
Advisor
이종덕
Issue Date
2007
Publisher
서울대학교 대학원
Keywords
유기 박막 트랜지스터OTFT펜타센pentacenePVAPVA이력현상hysteresisbias stressbias stress유기 회로organic circuit
Description
학위논문(석사) --서울대학교 대학원 :전기. 컴퓨터공학부,2007.
Language
Korean
URI
http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000043892

https://hdl.handle.net/10371/52518
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Master's Degree_전기·정보공학부)
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