Publications
Detailed Information
Fabrication and analysis of Si-through-via for stacked wafer-level MEMS packaging : MEMS 소자의 적층형 웨이퍼 수준 실장을 위한 실리콘 관통 비아의 제작 및 해석
DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | 전국진 | - |
dc.contributor.author | 정진우 | - |
dc.date.accessioned | 2010-02-09T14:57:20Z | - |
dc.date.available | 2010-02-09T14:57:20Z | - |
dc.date.copyright | 2007. | - |
dc.date.issued | 2007 | - |
dc.identifier.uri | http://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000045787 | eng |
dc.identifier.uri | https://hdl.handle.net/10371/53536 | - |
dc.description | Thesis(master`s)--서울대학교 대학원 :전기·컴퓨터공학부,2007. | en |
dc.format.extent | vii, 51 leaves | en |
dc.language.iso | en | en |
dc.publisher | 서울대학교 대학원 | en |
dc.subject | 관통 비아 | en |
dc.subject | Through-via | en |
dc.subject | 3차원 MEMS 소자 | en |
dc.subject | 3D MEMS devices | en |
dc.subject | MEMS 패키지 | en |
dc.subject | MEMS package | en |
dc.subject | 3차원 센서 | en |
dc.subject | 3D sensor | en |
dc.subject | 적층형 패키지 | en |
dc.subject | stacked package | en |
dc.subject | SiP | en |
dc.subject | SiP | en |
dc.title | Fabrication and analysis of Si-through-via for stacked wafer-level MEMS packaging | en |
dc.title.alternative | MEMS 소자의 적층형 웨이퍼 수준 실장을 위한 실리콘 관통 비아의 제작 및 해석 | en |
dc.type | Thesis | - |
dc.contributor.department | 전기·컴퓨터공학부 | - |
dc.description.degree | Master | en |
- Appears in Collections:
- Files in This Item:
- There are no files associated with this item.
Item View & Download Count
Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.