Browse

Fabrication and analysis of Si-through-via for stacked wafer-level MEMS packaging
MEMS 소자의 적층형 웨이퍼 수준 실장을 위한 실리콘 관통 비아의 제작 및 해석

DC Field Value Language
dc.contributor.advisor전국진-
dc.contributor.author정진우-
dc.date.accessioned2010-02-09T14:57:20Z-
dc.date.available2010-02-09T14:57:20Z-
dc.date.copyright2007.-
dc.date.issued2007-
dc.identifier.urihttp://dcollection.snu.ac.kr:80/jsp/common/DcLoOrgPer.jsp?sItemId=000000045787eng
dc.identifier.urihttps://hdl.handle.net/10371/53536-
dc.descriptionThesis(master`s)--서울대학교 대학원 :전기·컴퓨터공학부,2007.en
dc.format.extentvii, 51 leavesen
dc.language.isoenen
dc.publisher서울대학교 대학원en
dc.subject관통 비아en
dc.subjectThrough-viaen
dc.subject3차원 MEMS 소자en
dc.subject3D MEMS devicesen
dc.subjectMEMS 패키지en
dc.subjectMEMS packageen
dc.subject3차원 센서en
dc.subject3D sensoren
dc.subject적층형 패키지en
dc.subjectstacked packageen
dc.subjectSiPen
dc.subjectSiPen
dc.titleFabrication and analysis of Si-through-via for stacked wafer-level MEMS packagingen
dc.title.alternativeMEMS 소자의 적층형 웨이퍼 수준 실장을 위한 실리콘 관통 비아의 제작 및 해석en
dc.typeThesis-
dc.contributor.department전기·컴퓨터공학부-
dc.description.degreeMasteren
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Theses (Master's Degree_전기·정보공학부)
Files in This Item:
There are no files associated with this item.
  • mendeley

Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.

Browse