VLSI Implementation of a Soft Bit-Flipping Decoder for PG-LDPC Codes

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김종홍; 조준호; 성원용

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제16회 한국반도체학술대회
Low-density parity-check codes are known to show higher error correcting performance than conventional algebraic codes. However, the VLSI implementation of the codes has been considered very difficult especially when the row or column weight of them is high. In this paper, a projective-geometry(PG) LDPC code is implemented in VLSI employing the proposed soft bit flipping(SBF) algorithm. In addition to the processing unit sharing, the pipelining technique is employed to increase the decoding throughput. With the (1057, 813) PG-LDPC code, the implemented 4-bit SBF decoder consumes only a small area of 2.5mm^2, while providing the throughput of 6.5Gbps and good error performance close to the floating-point sumproduct algorithm(SPA) by 0.6dB at the frame error rate(FER) of 10^(-4).
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Others_전기·정보공학부
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