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Packing Buffer for Efficient Irregular Data access in SIMD Processors
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chang, Hoseok | - |
dc.contributor.author | Lim, Jieun | - |
dc.contributor.author | Sung, Wonyong | - |
dc.date.accessioned | 2009-08-04T06:45:45Z | - |
dc.date.available | 2009-08-04T06:45:45Z | - |
dc.date.issued | 2009 | - |
dc.identifier.citation | 제16회 한국반도체학술대회 | en |
dc.identifier.uri | http://kcs.cosar.or.kr | - |
dc.identifier.uri | https://hdl.handle.net/10371/6141 | - |
dc.description.abstract | The performance of an SIMD (Single Instruction Multiple Data) processor is bounded by the memory bottleneck; most of which is due to the overhead for preparing aligned vector data. In this paper, we have added a hardware unit to an SIMD processor to reduce the alignment overhead. The proposed packing buffer contains a small size multi-port memory block for which multiple addresses are generated by using a vector index register. Since the packing buffer has a small size, it requires neither complex hardware nor increased CPU cycle time. DSP benchmarks are used to measure the performance efficiency. | en |
dc.description.sponsorship | 이 논문은 지식경제부 출연금으로 ETRI와 시스템반도체산업진흥센터에서 수행한 IT SoC 핵심설계인력양성사업, 그리고 삼성반도체 주식회사의 지원을 받아 수행한 연구결과입니다. | en |
dc.language.iso | ko | en |
dc.title | Packing Buffer for Efficient Irregular Data access in SIMD Processors | en |
dc.type | Conference Paper | en |
dc.contributor.AlternativeAuthor | 장호석 | - |
dc.contributor.AlternativeAuthor | 임지은 | - |
dc.contributor.AlternativeAuthor | 성원용 | - |
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