낸드 플래시 메모리 오류 정정을 위한 병렬 BCH 복호기의 최적 설계

Abstract

In this work, we have developed a parallel BCH decoder for multi-level cell NAND flash memory. The decoder is designed to require minimum chip area as well as minimum power consumption for NAND flash memory applications. To achieve this goal, the parallle factor of each functional block is determined by using design exploitation techniques.